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16bit, 80Msamples/s ADC reduces noise in data conversion systems

Linear Technology has introduced a low-power, 16bit no missing codes, 80Msamples/s ADC (analogue-to-digital converter) that dissipates only 89mW. The LTC2259-16 provides a pin-compatible upgrade to the existing LTC2259-14 family of 14bit low power ADCs. The new device integrates two useful features for reducing digital feedback, including ABP (alternate bit polarity) mode and a data output randomiser. These features, in combination with low power, ease the task of designing with high-speed ADCs in a wide variety of applications, including HD broadcast cameras, IMO radar, Ethernet testers, portable test and instrumentation, software-defined radios, and cellular basestations. The device’s proprietary ABP mode inverts all of the odd bits before the output buffers to equalize the number of ones and zeroes switching. This method effectively cancels the large ground plane currents that contribute to digital feedback. In addition to the ABP mode, an optional data output randomiser is also available for reducing interference from the digital outputs. The randomiser decorrelates the digital output to reduce the likelihood of repetitive code patterns that couple back into the ADC input, causing unwanted tones in the output spectrum.

Operating from a low 1.8V analogue supply, the device offers signal to noise ratio performance of 73.1dB and SFDR of 88dB at baseband. Low jitter of 0.17psRMS allows undersampling of IF frequencies with enhanced noise performance. The LTC6406 is a recommended rail-to-rail ADC driver for maintaining new device's AC performance. The device's digital outputs can be set to full rate CMOS, DDR CMOS, or DDR LVDS. Double data rate digital outputs allow data to be transmitted on both the rising edge and the falling edge of the clock, reducing the number of data lines needed by half. A separate output power supply allows the CMOS output swing to range from 1.2 to 1.8V. Offered in a 6x6mm QFN package, the device includes a clock duty cycle stabiliser circuit to facilitate non-50% clock duty cycles, programmable digital output timing, programmable LVDS output current and optional LVDS output termination. These features combine to make the data transmission between the ADC and the digital receiver more flexible. The device joins a family of pin-compatible 14 and 12bit ADCs, with sampling rates ranging from 25 to 150Msamples/s, and power dissipation of 35 to 149mW, respectively.