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3D-FPGA technology trims FPGA costs, with timing-exact ASIC option

3D technologies as a means of driving forward FPGA technology are suddenly in vogue. In the case of the Tabula technology the 3-D is virtual; from Tier Logic, yet another FPGA start-up, comes a technology in which the 3-D structure is physical. Tier increases the effective logic density of its programmable array by taking the SRAM memory cells that configure the logic, out of the main array and placing them in a layer of amorphous silicon that its process deposits on top of the metal layers that interconnect the chip’s active devices. In other words, the transistors in the SRAM configuration memory are TFTs (thin-film transistors). As such, they have performance massively slower than the base process that carries the logic array; but as they only retain fixed information about the device configuration, TFT transistors are completely adequate.

Tier draws its logic structures to anticipate confi guration c onnections from the top of the metal-layer stack. By not adding the amorphous silicon layer, and making the confi guration connections in a further mask step, the company can offer an "instant-conversion" ASIC-like alternative product offering at reduced cost.

The new company says that users will be familiar with the architecture and tool fl ow when they design with the company’s Mobius tools as they have the same features as existing FPGA providers and the design fl ow is exactly the same. New or existing FPGA designs are synthesised, packed, placed, and routed into Tier Logic devices using industry-standard design tools, such as Precision Synthesis from Mentor Graphics. Mobius tools also create the bitstream for TierFPGA devices and the metal-mask data for TierASIC devices.

TierFPGA devices will be sampling in the second quarter of this year, with production qualifi ed in the forth quarter. However, TierASIC devices are available immediately and will be in volume production in the second quarter, for designs that could transfer from competitive FPGAs. Tier is attempting to entice designers to make that shift with an offer of free NRE for a $50,000 or greater production order.

Tier Logic, www.tierlogic.com.