3D-FPGA technology yields low-cost FPGAs and risk-free timing-exact ASICs

EDN Europe, 16 Mar 2010

3D technologies as a means of driving forward FPGA technology are suddenly in vogue. In the case of the Tabula technology (covered earlier here) the 3-D is virtual; from Tier Logic, yet another FPGA start-up, comes a technology in which the 3-D structure is physical. Tier increases the effective logic density of its programmable array by taking the SRAM memory cells that configure the logic out of the main array and placing them in a layer of amorphous silicon that its process deposits on top of the metal layers that interconnect the chip’s active devices. In other words, the transistors in the SRAM configuration memory are thin-film devices, or TFTs. As such, they have performance massively slower than the base process that carries the logic array; but as they only retain fixed information about the device configuration, TFT transistors are completely adequate.
Tier’s Logic structures are drawn to anticipate configuration connections from the top of the metal layer stack. By not adding the amorphous silicon layer, and making the configuration connections in a further mask step, the company can offer an “instant conversion” ASIC-like alternative product offering at reduced cost.
The new company says that users will be very familiar with the architecture and tool flow when they design with the Mobius tools from Tier Logic because they have the same features as existing FPGA providers and the design flow is exactly the same. New or existing FPGA designs are synthesised, packed, placed, and routed into Tier Logic devices using industry-standard design tools, such as Precision Synthesis from Mentor Graphics. Mobius tools also create the bitstream for TierFPGA devices and the metal-mask data for TierASIC devices.
TierFPGA devices will be sampling in Q2 of this year, with production qualified in Q4. However, TierASIC devices are available immediately and will be in volume production in Q2. Until the sample TierFPGA devices are shipping, Tier Logic is offering customers with existing FPGAs who wish to take advantage of immediate conversion to TierASIC devices a free NRE if they place an order for $50k or more of production. In addition, for an order of $100k or more, Tier Logic will also create a custom pin-compatible package to avoid customers having to alter existing PCBs. More information on this offer is available at www.tierlogic.com/launch.