3D-IC Testing with the Mentor Graphics Tessent Platform

January 30, 2012 // By Steve Pateras, Mentor Graphics
Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time. 3D chips connected via interposers are expected to go into production in 2011 or 2012 at Xilinx, Samsung, IBM, and Sematech [1]. Interposers are providing the logical first step to industrialization of 3D based on through-silicon vias (TSV)s. The next generation of 3D integration incorporates TSV technology as the primary method of interconnect between the die.
Mentor Graphics, 3-D testing, 3D-ICs, stacked ICs