Designing JESD204B converter systems for low BER

January 20, 2015 // By Ian Beavers & Jeffrey Ugalde, Analog Devices
Many real world sampling systems, such as test and measurement equipment, cannot tolerate a high rate of analogue to digital (ADC) or digital to analogue (DAC) processing errors. With the adoption of the new high speed serial digital interface link, known as JESD204B, between converters and FPGAs, the error rate within the digital transmission line cannot be ignored as a potential contributor to the overall BER.
Analog Devices, ADCs, converters, serial links, bit error rate, high speed, JESD204B