How to Achieve 10X Faster Power Integrity Analysis and Signoff

November 27, 2013 // By Jerry Zhao, Cadence
In our mobile computing era, system-on-chip (SoC) design has become much more complex, with challenges from complex design rules on advanced process nodes, low-power circuitry design techniques, and increasing circuit sizes. Power integrity is a crucial part of successful design signoff. This paper discusses a new tool that speeds power integrity analysis and signoff by 10X compared to other technology available, while still providing SPICE-like accuracy.
Cadence, SoC, Power integrity, SPICE