The proliferation of different, incompatible radios is a serious problem in military and aerospace situations, where a team may need units for airborne links, satellite communications, a base relay station, and an emergency transmitter, as well as application-specific roles such as for UAV operation. Each of these radio links serves a vital purpose, and leaving one out of the mix would deprive the operational team of a needed resource. Yet each radio carries a cost in size, weight, and spare battery needs. The problem is further complicated as new requirements and links are added to the list.
The solution is obvious, at least “on paper”: a universal full-duplex radio module which can be used across all platforms and dynamically reconfigured in the field as needed. The “one-radio” goal would lessen the load, provide flexibility and versatility, be efficient and so provide longer operating life from a single set of batteries, and thus provide significant SWaP (size, weight, power) advantages. That was the underlying premise of programs such as the JTRS (Joint Tactical Radio System) and software-defined radio (SDR) efforts.
But making the universal radio concept into a reality has proven harder than envisioned. While Moore's law has driven the availability of the high-performance, lower-power processors (including implementations on FPGAs) which are needed, providing the suitable integrated analogue front end (AFE) has been much more difficult. The demands on this functional block – which resides between the antenna and the processor and is the interface between the real-signal world and the digital world – are complex, varied, and stringent.
Until recently, a practical AFE for this type of versatile radio required an array of overlapping parallel channels, each designed to cover a particular segment of the RF spectrum and with bandwidth matched to the intended signal format. This approach, while feasible, is costly in terms of final PC board footprint, weight, power, and dollar cost.
High-performance single-chip AFE solution
A new RF IC is available which addresses the challenging SDR requirements and brings the SDR concept closer to reality. The AD9361 RF Agile Transceiver from Analogue Devices is a wideband, programmable front end supporting dual independent transceiver channels, to serve the fast-growing multiple-input, multiple-output (MIMO) segment as well as non-MIMO needs. The system processor can dynamically reconfigure key parameters (such as bandwidth and RF frequency) to match the application needs and thus deliver optimum results. The device also includes features to support frequency agile protocols.
This 10 × 10 mm chip-scale device, Figure 1, has user-tunable bandwidth from 200 kHz to 56 MHz along with other features and performance attributes which are needed to build a signal chain spanning 70 MHz to 6 GHz. Using this 2 × 2 direct-conversion component reduces the entire AFE into a single, relatively simple circuit. It interfaces with the host processor via an LVDS or CMOS port for speed and simplicity. Within the IC are 12-bit A/D and D/A converters, fractional-N synthesisers, digital and analogue filters, AGC (automatic gain control), transmit power monitoring, quadrature correction, and other critical functions.
Figure 1: The AD9361 is a 2 ×