Optimizing DDR Memory Subsystem Efficiency Part 1 – The Unpredictable Memory Bottleneck

March 23, 2016 // By Tim Kogel, Synopsys Inc.
DDR memory controllers provide arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, they provide Quality of Service features to satisfy the bandwidth and latency requirements from individual SoC components. However, numerous design parameters and configuration registers need to be set for a specific application to take advantage of these advanced capabilities. This whitepaper covers the challenges and the benefits of using virtual prototyping tools and best practice techniques for DDR memory controller configuration for differing SoCs.