Power-distribution issues occur in the simplest of circuits

November 13, 2013 // By Stever Sandler

A single tiny logic gate

The first case we’ll look at is a Fairchild NC7SZ04 ultra-high-speed inverter gate. This logic gate is a single inverter gate in an SOT-23 package, and it is part of a Picotest demonstration board designed to illustrate a PDN issue in a very simple low-power circuit (see Figure 1). The inverter gate is used as a buffer between a 10 MHz clock and a 50 Ohm port. The output impedance of the logic gate is approximately 20Ω, and R20 adds an additional 30Ω Ohms to total 50Ω in order to match the coaxial cable and input terminator on the oscilloscope. Resistor R18 is a 0805 package film resistor, which was increased from 0.2Ω (see Figure 2) to 1Ω in the tests here to make the device current signal easier to see, so the scaling is 1 V/A. This resistor does contribute to the issue, but it is not the dominant term.

Figure 1 Schematic of the logic gate buffer circuit, which converts the high output impedance, 10 MHz clock to a 50Ω output.

The very small section of the demonstration PCB that includes this logic gate is shown in Figure 2. The section shown is approximately 3 cm wide to provide some sense of scale. The decoupling capacitor for the logic gate, C14, is connected to the ground plane on the top side and three approximately 3-mm traces connect the capacitor to the 1Ω resistor and to the Vcc pin of the logic gate.

Figure 2 This small section of the board shows the logic gate, U3; along with the decoupling cap, C14; the current sense resistor, R18; the output coupling resistor, R20; and the AC coupling capacitor, C16.

The first thing that many will find surprising is that the edge speed of the logic gate is approximately 400 psec (see Figure 3). This picture also shows the AC voltage across the decoupling capacitor using a 4 GHz oscilloscope and a 4 GHz active probe. The probe and scope combination have a rise time of approximately 125 psec, so this measurement is not limited by the measurement bandwidth.

Figure 3 The output of the logic gate (top trace) and the AC voltage across the decoupling capacitor C14 (bottom trace)

The peak-to-peak voltage at the decoupling capacitor is 89 mV, which for a 5V part is not unreasonable. The voltage at the logic gate supply voltage pins is shown in Figure 4.

Figure 4 The AC-coupled voltage at the pins of the logic gate using the same oscilloscope and probe pairing.

The peak-to-peak voltage at the logic gate has increased to more than 1V, which is far beyond the maximum recommended range for most 5V devices. This particular part has a very wide operating range of 1.65V-5.5V. With a nominal 5V input, this voltage still comes very close to the maximum operating voltage.

A 1.5 GHz differential probe was used to measure the voltage across the 1Ω resistor and the frequency spectrum of the voltage. The measurement is shown in Figure 5; the spectrum analysis trace is the

When we think of a power distribution network (PDN), the issues that surround distributing power around a PCB, and the decoupling problems encountered, the first images that usually come to mind are FPGAs and CPUs. These circuits generally require ultra-low PDN impedance in order to maintain the appropriate voltage at the FPGA or CPU during the large dynamic current variations these devices present. This study focuses on a much smaller scale, addressing a very simple circuit that experiences related PDN issues. While the issues shown here may seem obvious to some, this is an excellent example of a very common problem.
Picotest, Sandler, PDN, decoupling