SoC design challenges in power management architectures with internal regulation

August 30, 2013 // By Snehal Rathi, Garima Jain and Shubhra Singh

Modern day SoCs are meant to support a number of functions in the field. This requires the SoC to have different IPs, peripherals etc. These subsystems in the design work on different voltage levels and are power hungry, also having different current requirements. Amongst these voltages, some are externally supplied, while others are internally generated.

For the internally generated voltages these SoCs may have more than one regulator catering to different needs, for example, high bandwidth/low drive and low bandwidth/high drive, but all regulating a single voltage supply (let this be the voltage for the digital IPs). When many of these digital functionalities get activated at the same time there are chances of current surges being seen on this internally regulated voltage supply. As standalone entities most of these regulators are flawless but when integrated into the SoC it is particularly important to see that this happens seamlessly.

Some critical issues that should be taken care of during integration are as follows:

a) The enabling of regulators from the Digital wrappers during the power-up phase of the SoC depending on the use case of regulators and its features.

b) The individual regulation levels of the regulators which ensure that the usage of the regulators is optimum and the system is immune to any dynamic current consumption profile changes.

c) Handling the disabling of regulators to avoid spikes on the current profile of supply during shut down of the device.

d) Regulators should support bypass feature for Test mode where an external control on all the supplies is needed.

Let us take up each of these issues in detail.

a) Power-up Phase

1) Masking of data coming from the digital domain

Consider the case when these regulators generate the supply on which the digital logic in the SoC works. Since this supply is building up in the power-up phase of the system, any signal coming from the digital domain is at a floating value, which can be at any level.

Hence this value has to be rejected at least until the digital supply in the system reaches a level above which the digital logic can be trusted. This level, of which the inputs coming from the digital domain should be masked, is the POR_REGULATED_SUPPLY which is about 0.7V (i.e. close to the threshold level of active devices).

Any logic which the system needs until this level is attained has to be safe-stated to ground level. This safe-stating is removed only when the POR_REGULATED_SUPPLY is reached. If this is not taken care of, then the system can be stuck in a loop where it will never come out of the Reset state.

2) Digital Wrapper of the regulators

The one problem that often arises in multi-regulated systems is related to the reuse of the logic, residing in the digital wrapper, for power-down of the regulators. It can skip the attention of most chip design and integration verification engineers that, though the design of these regulators, namely the MAIN and AUXILIARY regulator, is similar, the functions that they serve in the SoC are different.


This paper was a result of the many "bugs" found in some of the critical power-dependent SoCs the authors have uncovered in their experience. The authors examine these problems and present viable solutions and alternatives to prevent performance problems in these ICs.
Freescale, SoC design, power architecture, common problems