Synopsys: Foundation IP for 7nm FinFETs: Design and Implementation

April 18, 2016 // By Jamil Kawa, Synopsys Fellow

For all designers, the 7nm node promises to deliver significant area gains from the 10nm node and to exploit the cumulative experience in the lithography and reliability aspects gained in the development of the first three generations of FinFETs. As memory content can consume more than 50 percent of the system-on-chip (SoC) area, successful integration of memory in advanced-node SoCs requires a clear understanding of the FinFET architecture and its challenges.