Using Tessent Low Power Test to Manage Switching Activity

January 30, 2012 // By Giri Podichetty, Mentor Graphics

When planning for power-aware design-for-test (DFT) and creating production test patterns, these design techniques also should be considered and, in some cases leveraged, to manage power during test. Using the techniques outlined in the paper, scan shift switching can typically be reduced from 50% (normal level as even distribution on 1s and 0s) to 25% with minimal impact on test time. Capture switching activity can also be reduced by a significant amount, but the switching activity reduction as well as the impact on test time is highly design dependent. Designs with well-structured data paths and hierarchical, fine grained clock gating schemes can achieve capture switching activity of less than 10% with no coverage loss.

Today's advanced integrated circuit (IC) designs are increasing in complexity, with their seemingly endless progression to smaller geometries, ever increasing integration between analog and digital blocks, and diminishing supply voltages. Both this complexity and the need for energy efficiency in portable and wireless IC designs are increasing the level of concern over power use and power control during test. Attempts to manage power are being made at both the design and functional levels. Modular partitioning, power-domain gating, and clock gating are all techniques to manage dynamic and static power dissipation at the system level.
Mentor graphics, Tessent, IC design, modular partitioning