Akya reveals dynamically reconfigurable logic technology

EDN Europe, 28 May 2009

Akya is a UK-based start-up that is offering IC-designers IP (intellectual property) to include reconfigurable logic on their ASSPs or ASICs; Akya (say; Ak-eye-ya) will deliver both reconfigurable logic fabric, and IP blocks to execute commonly-required functions on that fabric. The Company’s CEO, Colin Dente, says that the reconfigurable logic can be a part of a larger chip design, or can form the basis of a complete IC. Akya calls its technology ART2, and says that its architecture separates dataflow and control logic to simplify design and implementation of reconfigurable structures.
Akya’s technology is, “Quite different,” Dente says, to other concepts that companies have marketed as dynamically-reconfigurable, “If I could think of another term to describe what we do, I would use it.” Dente explains that the architecture is not completely general-purpose, but that the company designed it to be, “just reconfigurable enough to do what’s needed,” in application areas such as audio/video codecs and communications-signal processing. The technology is, the company claims, particularly efficient at DSP (Digital Signal Processing) functions.
With Akya’s design tools – the approach can easily be learned, Dente says, by any engineer familiar with HDL-based design – you design a fabric that targets a specific applications area. This fabric is composed of, and draws on an IP library of, processing elements. These are, typically, at the level of arithmetic functions, rather than fine-grain, gate-level elements. To this, you add an address-sequencer, and programmable interconnect, to yield a set of processing resources that match your design. The design tools then assist you to create an explicit control flow for the design (that you can change after the silicon itself is finalised).
The reconfigurability materialises under the direction of the control flow; with every clock cycle you can completely re-configure the data path; you specify what action each processing element is to carry out on a cycle-by-cycle basis.
Although, Dente says, when you are doing the control programming, there is some similarity to writing code for a processor, the device you will be working with is not a VLIW processor. It does not write and read data to and from memory, and the minimal use of such transactions is one of the sources of Akya’s claims of very low power usage; “In [silicon] area and power, we are right at the custom-silicon end of the [design] spectrum,” Dente says, adding that portable and battery-powered products are targets for the technology. In part due to the architecture’s processing efficiency, for most telecoms or audio/video processing functions, clock speed is unlikely to be a constraint, Dente believes.
In terms of higher-level IP – the processing-block-level functions that will run on the reconfigurable fabric – Dente says that the company has some functions available, but expects more to appear as the result of co-operation with third-party suppliers. Akya’s initial target markets, Dente acknowledges, will be larger OEMs who will be capable of designing that level of IP for themselves.
By including reconfigurability, Akya says that you can reduce the risk of IC design, halve design time compared to RTL design, and modify existing designs – without changing the silicon itself – very quickly. With a reconfigurable block, you might make one mask set serve for several different designs, making a custom IC viable where it otherwise would not; the company offers a similar argument for the problem of adapting an IC to changing standards.
Akya supports ART2 with a development kit that features two high-level languages, one for data flow and one for control; Akya provides comprehensive training in the ART2 architecture compiler (artac). ART2 is available now; the first commercial chip incorporating the technology is in development and will be on sale, in an end-product, in 2010; Dente says that the company will have its own demonstration silicon later in 2009. The company also plans to incorporate its tools into the system-level-synthesis design flow of, “a major EDA company,” at a later stage.