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Altera jumps to 40 nm for Stratix IV

Power/function halved, density doubled – chips by year-end

Altera has announced a new generation of its most advanced series of FPGA – first parts will be available in the last quarter of 2008 – Stratix IV. With this round of product introductions Altera is giving equal billing to the matching HardCopy family, which also goes to generation IV. HardCopy chips are mask-programmed chips with with similar architectures to the Stratix parts, providing an ASIC-like conversion path to lower-cost silicon for volume users.
Both will be built in a technology that Altera and foundry TSMC have agreed to call 40 nm (in contrast to the more widely-discussed process node at 45 nm). In moving to 40 nm, the most significant performance metric for which the company optimised the chips is power. Power per gate is halved, and logic density approximately doubled, meaning that the largest part in the range has twice the logic of the largest Stratix III at 680k Logic Elements, for approximately the same power; or, if you use a smaller chip in the range, power will be halved. There will be two sub-families, one with high-speed serial transceivers that will operate up to 8.5 Gb/sec (48 on the largest part) and one without the transceivers but with more memory and DSP resources (the 680k LE part is in this group, with up to 22.4 Mbits of RAM and up 1360 18x18 multipliers: with transceivers on-chip, the largest family member has 530k LEs.). The Stratix IV devices will again have Altera’s Programmable Power Technology, in which the Quartus design tool identifies critical timing paths in the design and sets the logic blocks that they traverse to a faster/higher power state, while all other elements are placed in a lower-power condition. Performance in terms of logic speed is almost unchanged from Stratix-III: Altera says that the majority of its customers find that he logic speed is not a constraint.
The transceiver option will also extend to the HardCopy IV devices, which Altera now simply terms an ASIC solution. As before, the company guarantees that your Stratix design will transfer seamlessly to HardCopy for a lower-cost chip, for an engineering charge of around $400,000. Whereas in earlier technology, the biggest HardCopy device typically matched the average ASIC gate count of the same period, 40 nm allows Hardcopy IV to achieve densities several times that of the average contemporary ASIC. As opposed to the form/fit/function-compatible approach of earlier generations, you will now be able to obtain HardCopy devices in non-pin-compatible versions. The reason for the change is to allow users who do not need the full pin count of the programmable part to reduce the element of cost that is due to the package – significant for 1000-plus-pin packages. HardCopy III, matching Stratix III, will also employ 40-nm technology and Altera announced that family as part of the same release.
Options for designers who might previously have used ASICs are, Altera says, getting fewer; HardCopy becomes economic against the programmable equivalent at around 10,000 units, although that figure is highly variable. But with fewer and fewer large ASICs being designed, Altera believes its position grows stronger with the facility to develop a design in FPGA and carry out a conversion, at known cost, into an ASIC. Settings in the tool chain prevent any possibility of designing anything that would hinder a conversion from FPGA, but the company says that the restrictions imposed by making that choice are minimal. The first ASIC devices to go into 40 nm will be HardCopy III chip, at the end of this year. On fast designs, the company expects to see a power reduction of 75% compared to the programmable equivalent.
The corresponding software release is Quartus 8.0, released in June 2008, a feature of which is continued reduction in design compile time, achieved, Altera says, by algorithm refinement, multiprocessor support and incremental compile for design changes.