•  
• EDN Europe MAGAZINE
•  
• Free SUBSCRIPTION
• Subscription Renewal
• View Media Kit

• EDN
• EDN Australia
• EDN Asia
• EDN China
• EDN Japan

Analog/RF mixed-signal verification

Berkeley Design Automation has released a true SPICE accurate analog/RF mixed-signal verification solution based on co-simulation of its Analog FastSPICE circuit simulator with Verilog HDL simulators. The Analog FastSPICE Co-Simulation has been verified to deliver identical results 5x-10x faster than any other true SPICE accurate solution.
Analog FastSPICE Co-Simulation helps analog and RF design teams overcome mixed-signal verification challenges involving complex blocks (such as fractional-N PLLs, frequency synthesizers, and transmit and receive chains) that increasingly include complex digital logic; and nanometer CMOS ICs (such as system-on-chips (SoCs), wireless transceivers, power ICs, and data converters) that have a rich mix of digital logic and high-performance analog/RF circuitry. Also, the drawbacks of traditional SPICE in performance capacity are overcome by Analog FastSPICE Co-Simulation as it allows design teams to verify their analog/RF circuitry with true SPICE accuracy together with their digital logic using their standard Verilog simulator.
Analog FastSPICE Co-Simulation uses a standard Cadence Analog Design Environment based flow, including mixed-analog/digital debugging, and integrates with Verilog simulators including Cadence NC-Verilog, Cadence Verilog-XL, and Mentor Graphics ModelSim. The Analog FastSPICE circuit simulator uses Cadence Spectre and Synopsys HSPICE netlists and models and delivers results identical to that of the traditional golden SPICE simulators, but 5x-10x faster and with 5x-10x higher capacity. The results are foundry certified down to 45nm.