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BAKER’S BEST: From high to low frequencies with IBIS

One challenge that high-speed-digital-system designers have is tackling overshoot, undershoot, mismatchedimpedance ringing, jitter distribution, and crosstalk problems on their PCBs (printed-circuit boards). These problems fall into the category of signal integrity. Many highspeed- system designers use the IBIS (input/output-bufferinformation- specification) modeling language to anticipate and solve signal-integrity problems. This modeling language has been around since the early 1990s and has evolved into a formal standard: EIA-ANSI 656-B (www.eigroup.org/ibis). This standard is alive and well, and the IBIS consortium released Version 5 in August 2008. IBIS uses I-V (current-to-voltage) and V-t (voltage-to-time) data tables to describe a device’s I/O-pin characteristics. Manufacturers generate these tables by simulating or measuring their devices’ I/O cells.

This type of simulation tool is necessary for high-speed designs that now require clock rates of up to 20 Gbps. The simulation times for IBIS are considerably shorter than those of Spice, and the results are equally accurate. It takes days or weeks for a large PCB system to complete a transistor-level Spice simulation, whereas an IBIS simulation takes minutes or hours to execute. From an IBIS simulation, you can generate transmission-line responses and eye diagrams.

Customers are now asking for IBIS support with lower-frequency devices, with clocks that operate at frequencies lower than 40 MHz. Even at the lower frequencies, digital-signal edge rates cause signal-integrity issues. These fast edge rates can be responsible for clock signals that ring, causing a misinterpretation of a command or even an unexpected gain of two from an ADC. IC manufacturers have sophisticated analog Spice macro models for precision devices, but they are just catching up with the IBIS digital- I/O-model library. Figure 1 illustrates an example in which an IBIS-model simulation would be useful.

In this circuit, the designer has not paid attention to line impedances. The figure shows the measured results at an ADC in the system. The ADC and processor reside on their respective boards, and the designer simply connected the two boards through 1m Category 5 twisted-pair cables. The frequency of the clock signal from the processor is 2.25 MHz (CH3). The ADC uses this signal to synchronize the transmission of data back to the processor (CH2).

Initially, the designer thought that the low clock speed between these two devices would not cause termination problems. However, the termination used in this circuit creates signals that exceed high and low thresholds, causing ringing and degraded eye diagrams. IBIS simulations to the rescue! Save time and reduce costs. Identify problem digital circuits before turning your circuit into hardware.