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Baker's Best: Third round: Look at repeatability

System repeatability differs from system accuracy. With system repeatability, you compare the data from conversion to conversion. The specification that helps define repeatability is noise. For an analog device, such as a PGA (programmable-gain amplifier) or an ADC driving an amplifier, you take the noise-density performance at a frequency one decade less than the bandwidth of the device and multiply that value by the square root of the closed-loop bandwidth and (π/2). The multiple of the square root of (π/2) accounts for the noise in the region beyond the device’s bandwidth. The equation for this calculation is available with the online version of this article at www.edn.com/100624bb.

When calculating the total noise in a system, you can use an rms (root-sum-square) formula to combine these noise sources at the input of the circuit. The equation for this calculation is also available at www.edn.com/100624bb.

If you allow only less than 0.5 bit of error, the PGA-SAR (successive- approximation-register) system can achieve 12-bit repeatability with an analog gain to 16V/V. The rms noise density at 10 kHz of the PGA116 and OPA350 in this circuit is 12 and 5 nV/√Hz. The ADC’s contribution to noise is 26.9 μV rms.

The PGA-SAR system cannot meet a 12-bit level of repeatability with PGA gains greater than 16V/V (Table 1). What about a delta-sigma system, however? When it comes to noise, the delta-sigma converter relieves the board designer from tedious analog calculations. For the ADS1258, the effective resolution is 19.5 bits. The translation of 19.5 bits of resolution into repeatable volts in a 5V system is equal to 12 μV rms of noise. Regardless of the process gain for the delta-sigma converter, the 12-μV-rms noise level applies to the converter’s performance across all gains 1.258(Figure 1, available with the online version of this article at www.edn.com/100624bb). This performance differs from that of the PGA-ADC circuit in which the PGA’s gain affects the noise level.

If you look at the delta-sigma system from an input perspective, you can understand the size of the system’s LSB (least-significant bit). When the process gain is one, the RTI (referred-to-input) system LSB size is 1.22 mV, with a noise level of 12 μV rms. As the process gain increases, the system’s LSB decreases and the RTI noise remains constant. For instance, when the process gain is 128, the theoretical RTI LSB system is 9.54 mV, and the delta-sigma converter’s noise level is still 12 μV rms. If you look at the delta-sigma converter in terms of noise in Table 1 (columns 6 and 7), you can see a good 12-bit system up to a process gain of 32.

The repeatability of the PGA-SAR system produces a 12-bit-ready system with analog gains of one to 16V/V. The repeatability of the delta-sigma system produces a 12-bit-ready approach with process gains of one to 32. In this evaluation, the delta-sigma system slightly surpasses the noise performance of the PGA-SAR system.

As you think about the speed, accuracy, and the repeatability performance of the PGA-SAR system and a delta-sigma converter, from the discussions in this column and my previous three columns (references 1 through 3), which system would you now select for your application circuit, or is there more to consider here? Send your thoughts to me at ti_bonniebaker@list.ti.com.

REFERENCES

Baker, Bonnie, “Comparing SAR and delta-sigma ADCs’ throughput times,” EDN, April 22, 2010, pg 18, http://bit.ly/b3ZyHM. Baker, Bonnie, “The best solution brings accuracy,” EDN, May 27, 2010, pg 18, http://bit.ly/cJIj51. Baker, Bonnie, “System or technology dictates ADC choice,” EDN, March 18, 2010, http://bit.ly/90m15j