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Cadence and Mentor create free, open-source SystemVerilog methodology

In an effort to make it easier for users to create interoperable SystemVerilog verifi - cation fl ows, Cadence Design Systems and Mentor Graphics have jointly created—and are announcing that they will standardize on—the free, opensource OVM (Open Verifi cation Methodology). Steve Glaser, corporate vice president of marketing in the verifi cation division at Cadence, and Dennis Brophy, director of strategicbusiness development at Mentor, say that each EDA vendor offering SystemVerilog simulation fl ows has so far developed its own guidelines. Users must adopt these guidelines to develop verifi cation IP (intellectual property) for their fl ows. Mentor has offered the AVM (Advanced Verifi cation Methodology), and Mentor has contributed the UVM (Unifi edVerifi cation Methodology).

“Our customers have noticed that we’ve continued down this path of using our own proprietary, company-centric methodologies because they have to support N number of ways of doing things on N
N number of tools, which is making their job of porting verifi cation information a challenge,” says Brophy. “What we have beendoing is hampering design collaboration.”

Today, for example, a user could develop a piece of VIP (verifi cation IP), such as a SystemVerilog testbench or a transaction-level or RTL (register-transfer-level) model using one vendor’s format, but that VIP might not easily work in the other vendor’s System- Verilog simulation environment. “Users would essentially have to do the work themselves and build a bridge between the two vendors’ environments to make the VIP work in the other’s tool environment,” says Brophy. “The new OVM will eliminate the need for users to create that bridge on their own. We are enabling a truly interoperable VIP environment, promoting language interoperability and enabling data portability across multiple simulator platforms to deliver on the promise of SystemVerilog and open up a healthy and vibrant designand-verifi cation community.”

The new OVM is a superset of AVM and UVM, and Cadence and Mentor each dedicated developers to combine the best of both worlds to create OVM. The OVM deliverables include the OVM Methodology, which comprises how-to documentation, examples, and code snippets, and an OVM class library— essentially the buildingblocks to develop VIP.

Glaser and Brophy say that the OVM will allow customers and third-party providers of VIP to create testbenches and models in one format that will run in any OVM-compliant tool environment. “We tried to look at this problem quite holisticallyand said that to enable this methodology, we had to standardizeon an open set of functionalbuilding blocks, calledclass libraries. But there area lot of methodological implicationsthat then connect intoeven higher-level library functionsand even into the waythat tools need to interpret dataand the way that customersneed to take IP from differentsources and confi gure it for differentparameters. They thenstart operating it, controlling it,and being able to get messagesback,” says Glaser. “Thereare a lot of considerations forplug-and-play IP from multiplesources as well as thepath from block to chip to system-level reuse, which tends tobring in other languages suchas SystemC.” Brophy and Glaserclaim that OVM addressesall those issues and fully complieswith the IEEE OpenVeriloglanguage standard 1800-2005.

At least initially, the new methodology is a direct competitor and a competitive response to Synopsys’ (www. synopsys.com) proprietary VMM SystemVerilog guidelines, which also comply with IEEE 1800-2005. Synopsys has been a proponent of SystemVerilog and, some would say, the front-runner in the market ever since a few years ago when it acquired Co-Ware Design Automation, the company that originally developed SystemVerilog. But the VMM, say Glaser and Brophy, has been less than open and has lacked signifi cant links into SystemC. (Industry participants viewed SystemVerilog and SystemC as competing languages when they debuted a few years ago.)However, both Brophy and Glaser claim that Synopsys hasin the past declined to join anyopen SystemVerilog efforts.Synopsys and all other vendorsare free to adopt the OVM atany point, and broad adoptionof a single viable SystemVerilogmethodology would helpdesigners use their multivendorSystemVerilog-tool fl owsand would likely increase theuse and general sales of SystemVerilogtools and methods.“We think OVM will be a greatstep toward speeding up theadoption of SystemVerilog andadvanced verifi cation methodologies,”says Glaser.

Both companies had to modify their SystemVerilog simulation environments so that they could run VIP created using the OVM guidelines. Both companies have verifi ed that their simulation platforms, Mentor Questa and Cadence Incisive, can run VIP created with the OVM guidelines. Brophy notes that making the tools OVM-compliant wasn’t a painstaking process, so it should be fairly easy for other vendors to make their toolsOVM-compliant.

The companies are offering the free OVM as the Apache 2.0 open-source license. The companies will initially offer it to selected customers in the third quarter of this year and are planning to make the production release—which includes the methodology and supporting library—in the fourth quarter of this year. Initially, users will be able to download Apache 2.0 from Cadence’s and Mentor’s Web sites, but plans are in the works to eventually make it available from adedicated Web site.

Cadence Design Systems, www.cadence.com.

Mentor Graphics, www.mentor.com.