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Cadence improves predictability for nm-chip designs

At 65-nm-and-below, tools become more process-variability-aware

For chip designers working at advanced process nodes, Cadence has made a series of upgrades to its tool flow. At nanometre scales, process variability – the spread of electrical characteristics, relative to those intended by the designer, that arise from the inherent uncertainties in the manufacturing process – become very significant. Parasitic electrical effects, in particular, become large compared to the wanted parameters. You can carry out a design, then run a full parameter extraction and quantify those parasitic component values – but the re-design loop to correct them, in today’s volume-product design schedules, becomes unacceptable in terms of both time and cost. In the IC 6.1.3 release of the Virtuoso custom design platform, by using a model-based approach to the layout process in which the model contains detailed information relating process spreads to initial designed geometry, Cadence has been able to create a concurrent design flow in which the software is able to estimate – to, the company says, a high level of accuracy – parasitics in the as-manufactured silicon, at the time the chip layout is first defined. You will still carry out a full parameter extraction and simulation as a verification step, but it should now reveal many fewer unpleasant surprises. “Foundry-endorsed rule and model-based solutions are critical for 45-nm success,” Cadence says. In designing mixed-signal chips, the Analog Design Environment GXL within this release of Virtuoso comes into play; with fore-knowledge of parasitic effects the design-centering of component values can take the parasitics into account and design for maximum yield across process spreads. The Virtusos offering is integrated with the Cadence Multi-Mode Simulation technology in the new MMSIM 7.0 release. Cadence has reduced the time taken to execute detailed analogue simulations in this release with the “turbo technology” that is now part of its Spectre simulator. It achieves, the company says, five to 20-times faster run times, partly by taking advantage of multi-core computing platforms, without making and approximations to speed the mathematical analysis, while retaining “golden” simulator accuracy of results. You will see a performance increase even on single-core hosts, Cadence says.