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Characterizing noise in high-performance voltage-reference ICs

MEASURING THE NOISE PERFORMANCE OF A MODERN VOLTAGE REFERENCE REQUIRES SPECIAL MEASUREMENT TECHNIQUES.

Voltage-reference stability and noise frequently define the measurement limits of instrumentation systems. In particular, reference noise often sets stable resolution limits. Reference voltages have decreased with the continuing drop in system power-supply voltages, making reference noise increasingly important. The compressed signal-processing voltage range mandates a commensurate reduction in reference noise to maintain resolution. Noise ultimately translates into quantization uncertainty in ADCs, introducing jitter in applications such as scales, inertial navigation systems, infrared thermography, digital voltmeters, and medical-imaging apparatus. A new voltage reference has the accuracy and temperature coefficient that is typical of high-grade, low-voltage references. However, no other low-voltage electronic reference can equal the new device’s 0.1- to 10-Hz noise (Table 1).

You must use special techniques to verify such a part’s extremely low noise. A straightforward approach appears simple, but the practical implementation represents a measurement with a high order of difficulty (Figure 1). This 0.1- to 10-Hz noise-testing scheme includes a low-noise preamplifier, filters, and a peak-to-peak noise detector. The preamplifier’s 160-nV noise floor requires special design and layout techniques. A forward gain of 1 million permits conventional instruments to provide a readout.

The 1300-µF-capacitor/1.2-kΩ-resistor combination strips the reference’s dc potential (Figure 2). The ac content goes to transistor Q₁. Amplifier A₁ dc-stabilizes low-noise JFETs Q₁ and Q₂. Amplifier A₂ provides a single-ended output. Resistive feedback from A2 stabilizes the configuration at a gain of 10,000. A₂’s output routes to amplifier-filter A₃/A₄, which provides a 0.1- to 10-Hz response at a gain of 100. Amplifiers A₅ through A₈ comprise a peak-to-peak noise detector readout for a DVM (digital voltmeter) at a scale factor of 1V/µV. The peak-to-peak noise detector provides a highly accurate measurement, thus eliminating a tedious interpretation of an oscilloscope display. The indicated output instantaneously supplies a noise value to a monitoring oscilloscope. The 74C221 one-shot, which the oscilloscope’s sweep gate triggers, resets the peak-to-peak noise detector at the end of each 10-sec oscilloscope sweep. For a list of some useful low-level amplifiers for setting up and troubleshooting the circuit in Figure 2, see sidebar “High-sensitivity, low-noise amplifiers”).

To avoid errors resulting from saturation of the input amplifier, or from the introduction of new noise sources, you must select the—highly specialised—1300-µF input capacitor for its low leakage, using only the highest-grade, wet-slug 200°Crated tantalum types. The capacitor operates at a small fraction of its rated voltage at room temperature, resulting in lower leakage than its specification indicates. When evaluating leakage, you should note that the capacitor’s dielectric absorption requires a 24-hour charge time to ensure meaningful measurements (Figure 3). You determine capacitor leakage by using the following procedure:

1. Turn off the microvolt meter.
2. Connect the 3V battery stack.
3. Wait 24 hours.
4. Turn on the microvolt meter.
5. Read the capacitor’s leakage, where 1 nA equals 1 µV.

The yield to the required 5-nA leakage should exceed 90%. This high yield is most welcome because capacitors of this class sell for almost $400 each. A more palatable alternative may exist, however. Selected commercial-grade aluminum electrolytics can approach the required dc leakage, although their aperiodic noise bursts are a matter for concern. The input capacitor and its associated low-noise, 1.2-kΩ resistor are fully shielded against external-noise pickup.

You must carefully prepare the low-noise, gain-of-10,000 preamplifier because it is crucial to the noise measurement. JFETs Q₁ and Q₂ differentially feed A₂, forming a simple lownoise op amp. The 100-kΩ/10Ω pair provides feedback that sets the closed-loop gain at 10,000. Although Q₁ and Q₂ have low-noise characteristics, they suffer from high offset and drift. A₁ corrects these deficiencies by adjusting Q₁’s channel current through Q₃ to minimize the Q₁/Q₂ input difference. Q₁’s skewed drain values ensure that A1 can capture the offset. A₁ and Q₃ supply the necessary current into Q₁’s channel to force offset within about 30µV. The JFET’s gate-to-source voltage can vary over a 4-to-1 range. Because of this situation, you must hand-select the JFETs for 10% gate-to-source voltage matching. This matching allows A₁ to capture the offset without introducing significant noise. You must enclose Q₁ and Q₂ in an epoxy pot to thermally mate them and ensure a timelag response to a time constant much greater than A₁’s dc stabilizing-loop rolloff. This thermal management of the JFETs prevents offset instability and hunting in A₁’s stabilizing loop from masquerading as low-frequency noise.

A shielded can completely encloses the A₁/Q₁/Q₂/A₂ assembly and the reference under test (Figure 4). You should provide additional shielding to the input capacitor and resistor. The resistor’s wirewound construction has low noise but is susceptible to stray fields. The reference under test is socketed below the large input-capacitor shield and the JFET input amplifier’s associated components. Because Q₃ is a heat source, you should place it away from the JFET PCB’s (printed-circuit board’s) lands, which prevents convection currents from introducing noise. The amplifier’s ±15V power enters the enclosure through banana jacks. A 9V battery powers the reference under test to minimize noise and ensure freedom from ground loops.

The gain-of-100 filter and the peak-to-peak detector circuitry occupy a separate board outside the shielded can. You should minimize board leakage to the peak-detecting capacitors with guard rings or a flying-lead/Teflon standoff construction.

Peak-to-peak-detector design considerations include using JFETs as peak-trapping diodes to obtain lower leakage than conventional diodes afford. Diodes at the FET gates clamp reverse voltage, further minimizing leakage. Diode-connected JFETs’ superior leakage derives from their small gate-channel junction. In general, JFETs leak a few picoamperes, whereas common signal diodes, such as the 1N4148, leak approximately 1000 times more current, which you measure in nanoamperes at 25°C.

The peak-storage capacitors have a highly asymmetric chargedischarge profile, necessitating the use of low-dielectricabsorption polypropylene capacitors. Teflon and polystyrene dielectrics are even better, but Teflon capacitors are expensive and have an excessively large size at 1 µF, and the sole manufacturer of polystyrene film has ceased production. Oscilloscope connections through galvanically isolated links prevent ground-loop corruption. An isolated probe supplies the oscilloscope’s input signal. You should interface to the sweepgate output with an isolation-pulse transformer (see sidebar “Power, grounding, and shielding considerations” in the Web version of this article at www.edn-europe.com/article. asp?articleid=3400).

You must characterize circuit performance before measuring the noise of the reference under test. You can verify the preamplifier stage for greater-than-10-Hz bandwidth by applying a 1-µV step at its input with the reference disconnected while monitoring A₂’s output. A 10-msec rise time indicates a 35-Hz response (Figure 5). This approach ensures that the circuit supplies the entire 0.1- to 10-Hz noise spectrum to the succeeding filter stage. Oscilloscope plots reveal the peak-to-peak-noisedetector operation (Figure 6).

You measure the noise floor of the circuit by replacing the reference under test with a 3V battery stack. Dielectricabsorption effects in the large input capacitor require a 24-hour settling period before you take a measurement. The circuit’s oscilloscope output shows 160-nV, 0.1- to 10-Hz noise in a 10-sec sample window (Figure 7). Because noise adds in rootsum- square fashion, this output represents an approximately 2% error in the LTC6655’s expected 775-nV noise figure. Placing the root-sum-square-correction switch of Figure 2 in the appropriate position during reference testing accounts for this term. The resultant 2% gain attenuation corrects the reference under test’s output-noise reading to the first order. A strip-chart recording of the peak-to-peak noise detector’s output over six minutes shows less than 160-nV test-circuit noise (Figure 8). The circuit resets every 10 sec. A 3V battery biases the input capacitor, replacing the LTC6655 for this test.

You can observe the LTC6655’s noise after the 24-hour dielectric-absorption soak time (Figure 9). With the root-sumsquare correction enabled, the noise is within 775 nV p-p in this 10-sec sample window. The circuit’s verified low-noise floor makes it highly likely that this data is valid. You can apply this approach to measuring any 0.1- to 10-Hz noise source, although you should re-establish the root-sum-square error-correction coefficient for any given noise level.

AUTHOR’S B IOGRAPHY

Jim Williams is a staff scientist at Linear Technology (www.linear.com), where he specializes in analogcircuit and instrumentation design. He has served in similar capacities at National Semiconductor, Arthur D Little, and the Instrumentation Laboratory at the Massachusetts Institute of Technology (Cambridge, Massachusetts). He is a former student of Wayne State University (Detroit, Michigan).