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Clock tree design service enables reduced BOM costs

Silicon Laboratories has announced an online Clock Tree Design Service that gives customers quick access to experienced applications engineering team to provide custom timing architecture proposals that simplify design, reduce BOM costs and minimise risk during development. When combined with short component lead times of two weeks or less, the company's clock and oscillator family is designed to accelerate customers' time to market. Performance-sensitive applications often require a combination of oscillators, clock generators and clock buffers to provide critical reference timing to high-speed SerDes devices, FPGAs, processors, data converters (ADC/DACs) and DSPs (digital signal processors). Not only is individual timing component selection critical, but system-level requirements also need to be taken into account to optimise performance. The design service enables customers to enter their system-level timing requirements using a web-based utility, specifying multiple parameters including the number of clock inputs and outputs, input and output frequencies, signal formats and clock jitter. The applications engineering team reviews the requirements and provides a timing architecture optimised for performance, cost and lead time.

Timing proposals are provided in three business days, providing rapid feedback to customers. The company’s extensive timing portfolio and online customer support capabilities accelerate time to market and streamline the development process. Also offered is a clock Builder web utility to enable customers to quickly develop custom, application-specific clock generators that support any combination of user-specified input/output frequencies. The company’s custom oscillator utility enables developers to specify a custom oscillator, build a part number and order samples in minutes.