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CPLD autonomously awakens battery-powered system

A common industrial and consumer application is a system that samples an environmental condition, for example GPS (globalpositioning- system) location, voltage, temperature, or light, at a wide interval, such as once every minute. This type of system is becoming increasingly wireless and battery-powered; it wakes up every minute, takes a sample, transmits data to a central data-collection terminal, and then goes back to sleep. This Design Idea uses a small portion of an Altera (www.altera.com) EPM240- T100 CPLD (complex programmablelogic device) with a few discrete capacitors, resistors, diodes, and MOSFETs to autonomously wake a CPLD-based system from a full power-down state to an “on” state using an RC-timer circuit.This approach results in minimal power consumption during sampleswhen the power is on and betweensamples when the system, except forthe RC circuit, is effectively off.

Figure 1 shows the basic CPLD on/ off timer. Q1, an IRLML6302 P-channel MOSFET, is the power-control switch for the system. When the gate node is at VCC, which R2 pulls up, the power to the CPLD and the entire system is off, leaving only the RC circuit to use a tiny amount of power. The CPLD comprises a control block, a 4.4-MHz internal oscillator, a 3-bitregister, and six I/Os.

Figure 2 shows the state machine of the control block. The outputs in the state box are high, and all others are low. The dashed line from powerdown to power-up represents the time delay, which the RC circuit comprising R1 and C1 measures when the system is off. Switch S1 turns on and initializes the circuit. When S1 closes, D2 drives the gate node low, consequently turning on Q1 when the gate voltage is 0.7V below VCC. The EPM240-T100 is then operating in the power-up state less than 200 sec after Q1 applies power. The power-up state drives the power node low, which holds the gate voltage at 0.7V, keeping Q1 on after the switch is open. The power-up state also drives the charge node to VCC. This action charges the negative terminal of C1 to VCC. Because reset
0, the control block goes to the reset state and Register 1 gets reset. Once S1 opens, the control block goes to the enable state and drivesthe enable signal to one.

The sample-and-transmit circuit then begins operation and drives the done signal to zero. Once the sample and transmit are complete, the done signal becomes one, and the control block goes to the save state. The save state charges capacitors C2 to CN based onthe value in Register 1. The save state is active for 100 sec,allowing the outputs to fully chargethe 10-F capacitors. After 100 sec,the control block goes to the powerdownstate, which stops driving thecharge and power nodes. R4 pulls thepower node high, leaving R2 to pull upthe gate node.

Once the gate node reaches VCCVTQ1 at about 2.3V, Q1 shuts off power to the system. All EPM240- T100 I/O is in a high-impedance state and does not affect the gate or charge nodes. The charge node starts at VCC and begins to discharge through R1 once power is off. Once the charge node drops to 2.3V, D1 pulls down the gate node. Once the charge node reaches 1.6V, the gate node reaches 2.3V, and Q1 turns on. The time for Q1 to turn on is slightly less than the  of R1 and C1. Off time equalsR1C1
100,0000.0001
10 sec.

The device powers up in the powerup state but moves quickly to the sample state. The sample state reads the value on capacitors C2, C3, and C4. These capacitors act as nonvolatile memory, storing the count of previous power cycles. If the Register 1 value sampled on C2 through C4 is less than 7, then the control block goes to increment, and the Register 1 value increments by one. Then, the control block again goes to the save state to charge C2 through C4 to a new binary value, 001. The device powers down again. On the eighth power cycle, or about 80 sec after power-up, the control block moves to the enable state, thus enabling a new sample-andtransmit sequence. This process repeats every 80 sec. You can change the period by adjusting C1 and R1 and by changing the Register 1 size and count between enable cycles. Based on an 80-sec period comprising eight smaller power-up samples, test, and power-down cycles, the duty cycle for power is less than 3%; therefore, this approach increases battery life by asmuch as 33 times.