•  
• EDN Europe MAGAZINE
•  
• Free SUBSCRIPTION
• Subscription Renewal
• View Media Kit

• EDN
• EDN Australia
• EDN Asia
• EDN China
• EDN Japan

CPLD design tools feature improved synthesis and power optimisation

Lattice Semiconductor has announced the immediate availability of Version 1.4 of its ispLEVER Classic design tool suite. The design software has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH 4000ZE CPLD fitter with improved power optimisation. Synplify Pro HDL Analyst provides designers a way to rapidly visualise high-level register transfer level Verilog or VHDL. Designers can cross-probe between the graphical diagrams and source code to ensure that the coding style they use is the efficient for the target CPLD. FSMs (Finite State Machines), for example, are popular functions designed into CPLDs. FSMs are automatically extracted by HDL Analyst and displayed graphically as a bubble diagram with state transition arrows and a table of state encodings. To minimise the dynamic power consumption of ispMACH 4000ZE CPLDs, the Classic 1.4 fitter now automatically enables the device’s Power Guard feature for unused I/O and clock resources to avoid unnecessary internal switching. The software also includes improved features and educational material for the popular ispMACH 4000 CPLD family.

The synthesis interface to the 4000 family has been upgraded with additional optimisation control and a means to reference a Synplify Design Constraints file for timing objectives. The software Online Help has been expanded to make designing with CPLDs easy and more efficient. Online Help now includes links to key technical “How To” topics for ispMACH 4000 architectural features and power estimation. A new, generic schematic library manual describes logic symbols that are portable across SPLD and CPLD device families. The software is bundled with the ispVM System 17.8 programming environment. The ispLEVER Classic is the design environment for the company’s CPLDs and mature programmable products. It can be used to take a device completely through the design process, from concept to device JEDEC or bitstream programming file output. In addition to the tool support for devices provided by the downloadable versions of Synopsys Synplify Pro for Lattice and Active-HDL Web Edition, devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL.