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Data converter features ADC architecture

Fujitsu Semiconductor Europe has introduced an 8bit CHAIS (Charge-mode Interleaved Sampler) ADC for optical transport designs based on coherent detection. The data converter supports data rates from 55 to 65Gsamples/s and is based on the ADC architecture as the company’s 56Gsamples/s CHAIS ADC in 65nm. It offers enhanced sampling rates, wideband input, low noise and enhanced resolution required for long-haul links with data rates of 100Gbits/s and higher over a single wavelength. Implemented in a 0.9V, 40nm CMOS technology, the data converter will support high FEC overheads for long reach. The fundamentals of the CHAIS architecture allows for scalability to high sampling rates for 400Gbit/s/1Tbits/s transport data rates and power dissipation that scales with small process feature size. Typical power dissipation for a single CHAIS ADC channel in 40nm is 1.2W, down 50% from the power per channel in 65nm. Scaling of ADC technology to small process nodes enable enhanced functionality in the DSP and a roadmap for small form factors for optical module designs. The four-channel CMOS design allows for efficient integration with coherent receiver digital cores, comprising large number of logic gates and a multi-terabit data transfer rate across the interface between core and ADCs. For the design of single-die transceiver SoCs in 40nm, the Fujitsu IP offers high speed 11Gbit/s SerDes, supports a range of protocols and data rates, and will include a complementary enhanced speed 55 to 65Gsamples/s 8bit DAC. Integrating enhanced performance, low jitter analogue IP with a large, high-current spiking DSP requires attention to signal routing and isolation of noise-sensitive circuits.