• National opts for familiar outline for DC/DC modules 25/1/2010

  National Semiconductor has entered the market for highly-integrated power modules with a range of step-down dc/dc converters in a new package. Some packages that other vendors have employed for such ....

  LFoundry to buy Atmel’s Rousset, France, wafer fab 18/12/2009

  LFoundry, the mixed-signal foundry based in Landshut, near Munich, has announced its intention to purchase Atmel’s wafer fab in Rousset, France. ....

  Thermal simulation simplifies avionics heatsink design 11/12/2009

  When designers calculate the thermal budget for their projects, and conclude that they require an external heatsink, in most cases they know how their product will be oriented respect to gravity. A conventional finned heatsink operates most efficiently ....

  Synopsys adds automated synthesis flow from Matlab’s “M” to RTL 8/10/2009

  Synopsys has introduced a logic synthesis flow that begins with algorithmic descriptions written in M language, and provides a route to implementation that does not require designers to re-code their ....

  Online tools compile and download code for Coretex M3 MCUs 21/9/2009

  ARM and NXP have announced a collaboration that will provide designers with an on-line platform for rapid evaluation of embedded microcontroller-based projects. ....

  Cypress extends PSoC with ARM & 8051 cores 14/9/2009

  Cypress Semiconductor designed its PSoC (programmable system-on-chip) devices to contain all of the functional blocks of a small embedded system; a microcontroller core, programmable logic, and configurable ....

  Akya reveals dynamically reconfigurable logic technology 28/5/2009

  Akya is a UK-based start-up that is offering IC-designers IP (intellectual property) to include reconfigurable logic on their ASSPs or ASICs; Akya (say; Ak-eye-ya) will deliver both reconfigurable logic ....

  Cadence links FPGA pin allocation to PCB layout tools 20/5/2009

  Designers who use today’s large FPGAs on their PCB face an increasing problem handling the pin-out and board tracking around the packages of those programmable devices. The FPGAs have large, sometimes very large, pinouts; they offer considerable flexibility ....

  Synopsys merges IC layout and verification tools 11/5/2009

  A continuing theme of developments in IC-design tools is that EDA companies combine or integrate successive steps of their design flow. It has almost become a flow in itself; the first stage of that flow is that the need for a particular tool becomes ....

  UPF achieves formal standardisation as IEEE 1801 20/3/2009

  The IEEE and the EDA-industry alliance Accellera announced today that the IEEE has approved a new standard, IEEE 1801, ''Standard for Design and Verification ....

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