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EDN.COMMENT: A different approach

Synchronous design is the prevailing orthodoxy in digital electronics today. From the moment you first express the desire to become a logic designer, you are taught synchronous: good, asynchronous:bad. Asynchronous logic will get you into terrible trouble, with race conditions emerging and no comforting clock to fall back on to tie everything together–or so the dominant mode of thinking today might say. It wasn’t always so; when logic designs were small, asynchronous designs were pretty much the norm. In part, clocked, register-based design models came along with escalating complexity and automated design flows. And it’s by no means universally true today; anecdotally, many designers will have heard that significant areas of large processors, such as those made by the Intels and AMDs of the world, have many functions implemented in asynchronous logic for reasons of performance. But those companies have large teams of highly-specialised designers who can invest the time it takes to craft such “extreme” solutions.

There are a few examples scattered through the industry of companies that apply asynchronous design to achieve the fastest possible performance or to reduce power. One such, that focuses on the specific problem of on-chip interconnect, is Silistix, www.silistix.com, based in Manchester, UK. Manchester University has a long-established thread of research in asynchronous techniques, that included building an ARMcompatible processor core in self-timed logic (the Amulet).

Silistix identifies the interconnect area as a key limitation in today’s designs. In today’s leading-edge processes, clock distribution over long lines across chips is becoming very difficult and, perhaps more important, unpredictable. Silistix’ solution? Make the interconnect channels self-timed, communicating between conventional cores, memories and other blocks that remain as synchronous-logic entities. One factor that may increase the appeal of this proposal is that, with the shift to viewing–and sourcing–the individual functional blocks of an SoC design as separate pieces of IP (intellectual property), each already tends to operate within its local clock domain.

Silistix has therefore crafted an offering in which it will construct a block of synchronous logic (asynchronous design, to these engineers, is a technique, not a religion) that sits immediately adjacent to each of your onchip functional units and interfaces to it. Each of those talks to its peers over a network-on-chip structure that is asynchronous. You derive both parts of the solution via an automated tool chain that begins with a specification of your communications requirements in a dedicated language. With asynchronous links you do not need to seek timing closure; and you avoid the almost-circular trap of adding complexity and power to make the interconnect bus work, then layering on yet more complexity and power to distribute clock signals to the registers along the bus. You still, in the selftimed version, need a form of “repeater” periodically placed along long lines between on-chip blocks: where you would place a register in synchronous logic, you use a pipeline latch. Each of those receives data, propagates it to its output with only basic gate-delay, and signals that it is ready to accept the next item of data. In aggregate, a complete asynchronous link operates in the same way; data “ripples” through the link with a latency of only a number of gate delays, and the link acknowledges successful receipt of the data; a data “handshake” propagates through the channel. Wire delay is the limiting factor in the throughput of a networkon- chip channel, but the technique is delay-insensitive.

Silistix claims that its techniques will reduce interconnect dynamic power by 90%, with an overall impact on chip power that depends on how much of your power budget is devoted to interblock communications; and increase interconnect performance by 50%. Perhaps even more significant, you no longer have to struggle to achieve timing closure on those aspects of your design. Is this, nevertheless, a fringe technology, an exotic technique for those forced to operate outside the mainstream? The company points to the fact that it can cite both part of its start-up funding, and an endorsement for the interconnect technology itself, from Intel.

You could, if so minded, see a wider message here. Re-visiting techniques and technologies that have fallen out of favour or out of the mainstream may provide a path to solving an intractable problem. But don’t expect to change the whole world’s thinking on the subject; if you have a solution to offer, present it where the pain is greatest, and you will have the greatest chance of changing the orthodoxy.