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EDN.comment: Need to know

Towards the end of 2011, I visited IMEC, the semiconductor and systems research organisation in Leuven, Belgium for its annual review and update meeting. As always, an impressive array of technologies was on display, and part of the presentation concerned progress in IMEC’s core activity, semiconductor process development. If ever-smaller figures preceding the unit “nanometers” immediately lead you to wonder whether you need to know, let me quickly summarise. Process geometries of 20-nm will be in production soon, and IMEC researchers do not appear to see any major impediments to progressing onwards through 14 nm, 11 nm and even smaller nodes.

As part of that, IMEC continues to believe that extreme-ultraviolet (EUV) continues to offer the best route to commercial-scale patterning of wafers at these dimensions. Current practice at, say, 28 nm calls for increasingly exotic optical tricks to persuade light of wavelength considerably greater than the drawn patterns, to print those same patterns. A new technology is needed, and a shift to much shorter wavelengths is looking like the best (but not the only) option. On a previous visit to the IMEC cleanroom, engineers were assembling the “alpha” EUV “tool”. Tool, in this context, is the jargon for the EUV version of a wafer stepper, and describes something about the same size as a mid-range motor home, but costing (order of) €100 million. ASML is making the EUV machines.

Such is the confidence of advanced process designers in their inexorable progress, that at the time of that previous visit, no EUV light source for the machine actually existed; but the plan said that one would show up in due course, and so it proved to be. This time around, the issue is throughput: the wafers- exposed-per-hour figure is steadily improving, the tools currently fall short of the rate needed for commercial production by a factor of “only” between five and ten (it was much higher) but no-one involved seems unduly worried that that gap cannot be closed.

All that being said, should we care? Silicon foundries equipped for sub-20- nm process nodes are not going to be on every street corner; the community of IC designers working at these dimensions is going to be small in number, at least for the immediate future. A fellow editor in the US recently asked the same questions of 3D (stackeddice) design tools; a great deal of effort is going into that area but again, should we care? (3D structures, through-wafer connections and related technologies is also an IMEC area of expertise: and ST Microelectronics is to lead a European project on the subject, see www.edn-europe. com/article.asp?articleid=5242)

It may very well be the case that the most advanced chip design, or multidie, system-in-package structures will remain the province of relatively few specialists. However, even if you do not have that intimate connection with the silicon, following these topics amounts to more than passing interest in exotic technologies. We are all affected to some extent by the economics of the semiconductor industry; the constant expectation of ever-more processing power for ever-declining cost drives product design and is underpinned in turn by the steady march of silicon process geometry.

Of 3D design, I am less certain; over many years, and whether they were called hybrids, or multi-chip modules, or systems-in-package, tightly-integrated assemblies of multiple chips have stubbornly refused to expand their reach beyond being niche – usually, expensive niche – products. Before long, we might find out if this attempt to revisit the idea can break out to massmarket applications.