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IC design

Imec & Cadence tapeout first test chip for 5-nm technologies

Nano-electronics research centre imec (Leuven, Belgium) and Cadence Design Systems, have announced first tapeout of a 5nm test chip using extreme ultraviolet (EUV) as well as 193 immersion (193i) lithography.


Fastest, highest-resolution DLP chipset for 3D print/lithography

With its latest micro-mirror-based light-steering chip, Texas Instruments says, applications developers can innovate with more than 4 million micromirrors to enable high throughput digital imaging applications.

IC design

DVCon Europe 2015 announces Technical Program

The Design and Verification Conference (DVCon) and Exhibition Europe (Munich, 11th & 12th November 2015) takes as its scope. “the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits.”