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Large-system rapid prototyping, software development & low-power verification from Cadence

By Graham Prophet & Julien Happich // Jul. 18, 2014

Large-system rapid prototyping, software development & low-power verification from Cadence

Added to Cadence Design Systemsí System Development Suite, the Protium rapid prototyping platform is configured to improve software development productivity, and includes verification according to the IEEE 1801 low power standard.

Protium operates with the Cadence Palladium XP II verification computing platform. System and semiconductor companies in the mobile, consumer, networking and storage segments can, Cadence says, use the system to address design challenges such as early software bring-up and reduced power consumption.


The hardware of the platform is FPGA-based: it employs Xilinx Virtex-7 2000T FPGAs, and is Cadence's second-generation FPGA prototyping platform for software development. It improves productivity by reducing prototype bring-up time by up to a claimed 70% versus alternative approaches. It comprises a four-fold increase in capacity over the previous generation, and support for up to 100 million gates. The platform enables software development and throughput regressions supported by a fully automatic flow and the capability to execute user-driven performance optimisations. The Protium platform also provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimises “tedious and error-prone” manual FPGA bring-up steps.


A key part of the process is mapping a design into the FPGAs, for which Cadence has written its own tools. In a discussion with EETimes Europe, Frank Schirrmeister, Group Director at Cadence Design Systems and responsible for product management of the Cadence System Development Suite, observed, “Typically with competing solutions, designers use the partitioning tools that are offered by the FPGA vendors, but these tools are [optimised] for designs that fit into one FPGA. So designers have to rewrite their RTL to map it across multiple FPGAs; they must also remodel their memory, and it can take them up to three months to bring up the FPGA prototype... by adding a software platform that takes care of this automatically, we bring down the set up time to a few weeks”.


Low-power analysis and verification is a key part of system and system-on-chip (SoC) signoff criteria, Cadence notes, addressing this by expanding Dynamic Power Analysis in the Palladium XP II platform beyond Common Power Format (CPF) support, adding verification and debug support for the IEEE 1801 standard. The Cadence System Development Suite now offers an integrated and consistent low-power flow for engineers using either of the power standards across the Incisive formal and simulation and Palladium platforms, with common power plan and metrics, and integrated debug analysis.


Cadence; www.cadence.com/news/protium



 
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