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Enhanced FPGA design tool suite

Lattice Semiconductor has announced the immediate availability of SP2 (Service Pack 2) for version 7.2 of its ispLEVER FPGA design tool suite. SP2 is an optimal update for users of LatticeECP3 devices, and also includes support for new LatticeXP2 devices. SP2 allows users of ECP3-70 and ECP-95 devices to design with assurance that the board-level behaviour of their design, such as simultaneous switching output noise, power and timing, will match what the tools report. SP2 also boosts DSP application performance in the LatticeECP3 devices. Design support for the LatticeECP3 FPGA family was first made available in the ispLEVER 7.2 SP1 design tool suite. With SP2, static timing analysis, power and SSO will report results that accurately reflect the behaviour of the actual production device. The PCS/SERDES calibration settings used for the supported IO protocols have been tuned to provide more robust behaviour. The sysDSP block support also has been enhanced to include higher performance modes of primitive blocks targeted at specific applications, such as FIR filters, decimators, interpolators, matrix multiplication and video applications. These modes are made possible by the enhanced cascade support in the LatticeECP3 devices’ sysDSP architecture.

Service Pack 2 also supports the recently announced industrial temperature qualified, non-volatile LatticeXP2 devices that are available in low-cost, small-footprint BGA or QFP packaging. The ispLEVER design tool suite provides a complete set of tools for all design tasks, including project management, IP integration, design planning, place and route, and in-system logic analysis. The ispLEVER tool suite is provided on CD-ROM and DVD for Windows, UNIX or Linux platforms. Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec’s Active-HDL Lattice Edition simulator is included for Windows. In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, which are included in the ispLEVER tool suite, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 family. Precision RTL synthesis support for LatticeECP3 devices requires an update that is available from the Mentor Graphics website.