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Enhanced memory signaling meets performance requirements of graphics and gaming systems

Rambus claims that it has enhanced differential signaling for SoC-to-memory interfaces to a 20Gbit/s and developed innovations, which can extend single-ended memory signaling to a 12.8Gbit/s. The company also developed innovations, which enable a seamless transition for memory architectures from single-ended to differential signaling as data rates rise to meet the performance requirements of future-generation graphics and gaming systems. The latest technology of Terabyte Bandwidth Initiative enables high power efficiency and compatibility to single-ended memory architectures, including GDDR5 and DDR3. With the addition of FlexMode interface technology, a multi-modal, SoC memory interface PHY, supporting both differential and single-ended signaling, can be implemented in a single SoC package design with no additional pins. The company has achieved a power efficiency of 6mW per Gbit/s when operating at 20Gbit/s in a 40nm-process silicon test vehicle. These innovations address critical system challenges to extending signaling rates by addressing power efficiency and compatibility needs.