Hosted by Accellera Systems Initiative, an organization with the mission to develop and deploy EDA and IP standards, the format of DVCon Europe 2016 is similar to the successful DVCon United States conference held for over 20 years in the Silicon Valley. The event, say the organizers, has, “... a highly technical focus on System and IC design, verification, and integration; DVCon Europe is a very practical and industry-focused conference on EDA standards and standardization.”
Two keynote speakers have been announced for the event; Hobson Bullman, General Manager of the Technology Services Group at ARM and Juergen Weyer, Vice President of Automotive Sales for EMEA at NXP Semiconductors will deliver addresses focused on advanced development flows and automotive technology trends, respectively.
Mr. Bullman will address the current methodology and infrastructure challenges being faced, and discuss solutions developed by ARM for delivering IP to a demanding partner base across a wide variety of markets. He will examine trends and evolving practices that maximize development effectiveness across large engineering teams. Mr. Weyer will leverage his considerable knowledge of the automotive semiconductor industry to present the design trends and technologies that he considers critical in this market. In his talk entitled “The Road Ahead for the Securely Connected, Self-Driving Car,” he will highlight ongoing developments and next-generation solutions to enable securely connected and self-driving cars.
From the Conference website;
In order to boost the interest, usage and development of electronic design automation (EDA) and intellectual property (IP) standards in Europe, this highly technical conference is organized to invite industry experts to learn and share best practices on:
- The application of system-level design and verification languages such as SystemC, SystemVerilog or e
- The use of SystemVerilog Assertions (SVA) or the Property Specification Language (PSL)
- Verification methodologies based on the Universal Verification Methodology (UVM)
- IP reuse, automation and integration standards based on IP-XACT
- Low power design and verification using the Unified Power Format (UPF)
General topic areas on Electronic System Level (ESL), Verification & Validation, Analogue/Mixed-Signal, IP reuse, Design Automation, and Low Power design and verification, will be highlighted in tutorials, papers, and poster sessions.
Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of EDA tools and IP integration.
DVCon Europe 2016 selects the best user experiences, high quality papers and presentations around best practices on the application of standardized languages, tools, and methodologies for design and verification such as SystemC, SystemVerilog, PSL, UVM, IP-XACT and many more.
DVCon Europe 2016 organizes technical workshops and tutorials on emerging EDA and IP standards, with highly educational content. Experts in the industry share on topics like UVM, SystemC and IP-XACT, with the fundamental concepts and practical usage of these standards explained, including examples and demonstrations.
DVCon Europe 2016 hosts a compact exhibition where the industry can meet to discuss EDA and IP tool and service solutions. Visit the exhibition for demonstrations, interactive discussions, and top vendor offerings.
More at; https://dvcon-europe.org