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FPGA-based prototyping tools incorporate incremental compilation technology

Synopsys has announced updates to its Identify and Certify FPGA-based prototyping tools. The software tools incorporate incremental compilation technology that accelerates implementation of design revisions, as well as automation to ease the partitioning of large designs into multiple high performance ASIC prototyping system boards. The latest release of the Certify multi-FPGA ASIC prototyping software produces static timing analysis estimates with post-route delay back annotation. It accelerates the ASIC design migration with support for encrypted DesignWare Library IP. It also obtains a complete resource analysis of multi-FPGA designs with the latest PCB trace impact analysis. A high degree of visibility inside the FPGAs of the prototyping system significantly optimises debugging efficiency, claims the company. The latest release of Identify RTL debugger understands the prototype operation with debugger results annotated in the RTL View of the Synplify HDL Analyst graphical analysis tool. It isolates the defects by tracing periods of signal activity with up to 64 times more sample buffer capacity. It also updates and implements design instrumentation faster with Synplify compile point technology by preserving design modules not affected by debug instrumentation.