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FPGA interoperated with PCIE gen3 switch for development of PCIE gen3 systems

Altera has interoperated its 28nm Stratix V GX FPGA with PLX Technology’s ExpressLane PCIe (PCI Express) Gen3 switch. The FPGAs feature up to four hard PCIe Gen3 x8 IP blocks, which support one, two, four and eight lane configurations and provide transfer rates up to 8Gbit/s per lane. Hardening the PCIe IP blocks in the FPGAs delivers a savings of over 100,000 logic elements when compared to alternative soft implementations, says the company. The hard PCIe Gen3 IP blocks embed the PCIe protocol stack into the FPGA and include the transceiver modules, physical layer, data link layer and transaction layer. The FPGA’s PCIe Gen3 IP targets PCIe base specification revision 3.0, 2.x, and 1.x. The Gen3 portfolio includes 11 devices ranging from 12 to 48 lanes and three to 18 ports with more configurations in development. The company claims that the FPGA portfolio provides customers with clearly differentiated solutions across its Arria V, Cyclone V, and Stratix V FPGA families and its HardCopy V ASIC series.