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FPGA IP completes solution for wireless backhaul networks

Wintegra provides upgrade path for higher density wireless backhaul solutions

Wintegra’s third generation Universal Front End (UFE3) IP core for high channel density wireless backhaul designs, when used with the company’s WinPath2 processor and PMC-Sierra’s TEMUX family of framer and mappers, provides an upgrade path for designers working to migrate voice-centric cellular solutions to high-capacity data-plus-voice capable designs. Carrier Ethernet is, Wintegra says, becoming the prevalent way of carrying this combined voice and data traffic between cell sites and central offices. Director of Technical Marketing Gordon Lawton describes wireless backhaul aggregation as one of the “hot” areas in telecoms at present. The UFE3 IP core plus Wintegra’s WinPath2 processors at the central office provides bi-directional conversion of 8064 legacy DS0 channels to Gigabit Ethernet, with Carrier Ethernet as the link to remote cell sites. The UFE3 enables a fully channelised application running any protocol including PWE3 (Pseudo Wire End to End Emulation), MC/ML-PPP (Multi-Class Multi-Link PPP), IMA (Inverse Multiplexing over ATM), or MFR (Multilink Frame Relay).
A typical example that Wintegra quotes takes an OC-12 channel (plus a reserve duplicate channel) on one side, into the PMC Sierra chip, which connects to an Altera Stratix II FPGA where the IP resides, and to the WinPath2 on the backplane side. Lawton stops short of calling the combined offering a reference design, because, he says, designers working in this space invariably produce solutions tailored to a particular specification; to that end, the IP core allows them to work with TDM interfaces and channel densities from 24xT1/E1, 1xOC-3/STM-1, 2xOC-3/STM-1 and up to 4xOC-3/STM-1 or 1xOC-12/STM-4, providing a glueless interface to PMC-Sierra devices including its latest TEMUX 336 and TEMUX 168 devices, which integrate 4xOC-3/STM-1 or OC-12/STM-4 and 2xOC-3/STM-1 framer and mappers respectively.
The UFE3 soft core is verified on the Altera Stratix II FPGA. Wintegra supplies it, for a per-project fee, in source code. A reference board is available from Wintegra featuring Altera’s Stratix II FPGA and PMC-Sierra’s TEMUX 336.