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FPGAs address demanding traffic management configurations

Xilinx announced the acquisition of Modelware, a provider of traffic management and packet processing silicon IP cores and reference designs that simplify system development and enable differentiation for networking applications supporting 10, 40, and 100G speeds. The company has also introduced an FPGA-based 100G traffic management reference design to quicken evaluation and implementation of high bandwidth packet processing applications.The acquisition enables Xilinx to deliver FPGA-optimised packet processing, switching, and traffic management solutions that address granular per-flow bandwidth provisioning as well as scalable traffic aggregation capabilities across the service provider, enterprise networking, and data center markets. Modelware’s solutions consists of optimised IP cores specifically tuned for Xilinx FPGAs and deployed across the spectrum of packet processing, switching, and traffic management systems. The company claims that customers can build 100G traffic management systems based around the Virtex-6 HXT FPGAs, which offer serial bandwidth through a combination of 6.6Gbit/s gigascale systems research center technology extrapolation transceivers and 11.18Gbit/s GTH transceivers. Xilinx’s FPGA architecture offers a range of choices through migration to its 28nm 7-series FPGA families. The Kintex-7 and Virtex-7 FPGAs support an array of memory controllers and high memory bandwidth to address demanding packet processing and traffic management configurations. The Kintex-7 FPGA family supports up to 32, 12.5Gbit/s transceivers whereas the Virtex-7 HT FPGA family offers up to 72, 13.1Gbit/s, in combination with up to 16 and 28Gbit/s transceivers.