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FPGAs reach for new application spaces

PROGRAMMABLE-LOGIC VENDORS HAVE ALWAYS GONE TO MARKET WITH A MESSAGE CENTRED ON—AMONG OTHER ASPECTS—FLEXIBILITY AND LOW UP-FRONT DESIGN COSTS. ON TOP OF THAT COME TARGETED IP OFFERINGS, PERFORMANCE METRICS THAT ARE MORE THAN A MATCH FOR MOST APPLICATIONS, AND A GROWING CONFIDENCE IN THE SECTOR’S ABILITY TO SECURE DESIGN WINS FOR PROGRAMMABLE TECHNOLOGY IN AREAS SUCH AS AUTOMOTIVE DESIGN AND CELLULAR BASESTATIONS.

In 2007, semiconductor industry analysts, notably Gartner group, were forecasting that the programmable-logic sector would end the year showing a slight decline in revenues. Data published so far in 2008 indicates that this view was probably correct: the numbers reflect a business trend that has seen the sector deliver higher volumes of product—and, given the increasing complexity of each range of devices, many more logic gates—but struggle to hold on to revenue levels as the cost per chip continues to fall. There is nothing particularly sinister in that for the PLD (programmable-logic-device) companies—much of the industry had a hard time with prices in 2007. For the programmable-logic companies, it means that in order to grow they have to put ever-increasing efforts into developing new market sectors, and into getting you, the designer, to consider them for functions you would previously have carried out with ASSPs or ASICs.

Replacing large ASICs has long been an objective for the PLD companies, and as the costs of designing a large SoC (System-on-Chip) continue to climb, one where they are claiming more successes. This is not all beneficial for them: for many years they have enjoyed a healthy—if modest-volume—business for the highest density programmable chips for use in ASIC prototypes and in hardware-emulation systems. Fewer big ASIC starts implies fewer prototyping exercises, so that sector is likely not the one that will expand the PLD companies’ business rapidly in the future—but neither will it disappear.

In the European region, it is not surprising to hear the PLD vendors say that one of the largest growth sectors for them over the last few years has been communications, despite the disaster of the 2001/2002 period. An example of the class of application in which PLDs are attempting to oust ASIC/ASSP solutions was on display at the recent Mobile World Congress in Barcelona. At that event, Xilinx demonstrated a reference design for implementing digital predistortion in the transmitter signal path of a wireless basestation. It bases the DPD (digital-pre-distortion) reference design on its Virtex family of platform FPGAs, driving amplifier stages that employ Freescale’s new RF power LDMOS devices for wireless infrastructure. Designers can adapt the DPD reference design to develop LTE, WiMax, WCDMA and TD-SCDMA multi-carrier systems.

IC POWER AND COST CONTROL

Xilinx bases its case on a detailed breakdown of both capital and operating costs for a basestation. Over 60% of the capital cost is in radio cards and power amplifiers; and PA (power-amplifier) efficiency is significant in the total energy that the basestation uses while in operation—put simply, in the electricity bill. Thus, a more efficient PA means lower operating costs. Basestation PAs for current and future digital-modulation schemes must exhibit very high linearity and be able to handle signals with high peak-to-average ratios. Traditional linear amplifier architectures that can do so are not power-efficient, hence the interest in architectures such as the Doherty configuration. Doherty amplifiers have two amplification paths: one for average signal levels and one to handle peaks. With issues such as cross-over distortion, you need to expend considerable effort to linearise the amplifier. The answer to this problem is pre-distortion: with prior knowledge of the characteristics of the PA, you can compute the distortion that your signal will suffer and apply the inverse function to the signal before it reaches the amplifier. But that is not a static computation—the transfer characteristics of the amplifier change over the long term due to aging effects, and in the short-term due to thermal, supply voltage and other conditions, even including semiconductor-device phenomena that affect performance depending on the immediately-prior-signal wave-shape. Consequently, you must monitor distortion products in the amplifier output and constantly adjust the pre-distortion computation. The architecture is, in effect, a complex blend of feed-forward and feedback compensation loops.

It is no surprise that this calls for a significant amount of signal processing and computation. The competitive analysis that Xilinx presents asserts that the conventional solution on a radio card needs five chips: a physical-interface SERDES IC, DSPs in both transmit and receive paths, a crest-factor-reduction chip, and an ASSP to handle the DPD calculation itself. You can get all of this into about one-third of a Virtex5 SX35T programmable chip, Xilinx says, at around one-third of the silicon cost and half the power. (This analysis is, Xilinx asserts, for a single-sector 15-MHz—threecarrier— UMTS radio card with diversity receiver.) The analysis also suggests that with fewer devices to attach to a board, reliability will also be higher—this is a significant factor, Xilinx says, as vendors look to a possible future scenario of large numbers of low-cost femtocells in the field, where high maintenance costs will be unacceptable.

As with all exercises at the upper end of the programmable-device market, Altera has a matching analysis for processing digitally-modulated signals. In a recent paper, Altera took as an example the filtering that a 2x2-order MIMO system needs at the symbol-processing level: 60% of the resources of a 1-GHz DSP, the company estimates. By using the multiple instances of hardware multipliers that exist in its FPGA architectures to implement parallel processing, you can do the same signal processing in a few per cent of one of its Stratix II devices. Other trends in radio-card design can only serve to increase the computational load still further: MIMO configuration of greater complexity than 2x2 or multiple-antenna beamforming and spatial multiplexing all come into play.

FIELD UPGRADES

Among the advantages of their products, programmable-logic suppliers have long quoted the fact that with programmability— the ability to perform in-place upgrades and firmware changes. In reality, the number of cases in which designers have fully exploited the opportunity for in-service, remotely executed firmware revisions have been limited. With nextgeneration wireless, however, the PLD companies may have found a sector in which the case is sound. Especially with respect to LTE (the long-term evolution of UMTS), design work is proceeding while the higer levels of the standard are still some way off from being stable. If it pays to embed your algorithm in hardware, and the algorithm is still evolving, it ought to be a positive factor if you can change the hardware on demand.

One of the enabling factors in the programmable logic’s move into the high end of communications has been the inclusion, on the periphery of the chips, of fast serial interfaces incorporating SERDES functionality. Lattice Semiconductor has made a special feature of this capability and in recent weeks it has announced that all five of its ECP2M FPGAs are now in volume production; they include a highspeed embedded SERDES I/O function, plus a pre-engineered Physical Coding Sublayer (PCS) block. Lattice declared at initial announcement that it intended this family to bridge the gap between lowcost and high-end FPGAs—where you could find the SERDES function previously. The company says it has integrated the SERDES into the ECP2M family for implementation in a cost-effective, power-efficient—power consumption as low as 100mW—quad-based architecture with 1 to 4 quads, depending on the size of the device. Each quad has four complete TX and RX SERDES channels and supports data rates from 270 Mbps to 3.125 Gbps. The company has also built a flexible PCS layer that includes 8b/10b encoding, an Ethernet-link state machine and rate-matching circuitry onto the chip. Lattice designed the SERDES/ PCS combination to support common packet-based protocols, including PCI Express, Gigabit Ethernet, Serial RapidIO and wireless-interface standards, such as OBSAI and CPRI.

Those high-end FPGAs offer fast serial I/O that will run even faster; Altera’s Stratix II parts have physical interfaces that will run at up to 6.375 Gbps, according to Ro Chawla, European marketing manager; the company has announced a capability to implement SERDES Framer Interface Level 5 (SFI-5) standard support in Stratix II GX FPGAs, providing a 40-to-50-Gbps interface for optical-communications applications. Even in today’s market, that is at—or beyond—the limits of what many designers will require, and when the company introduced its Arria GX series of low-cost transceiver-based chips some months ago, it implemented what Chawla describes as a tuned version of the Stratix transceiver, running at up to 3.125 Gbit/sec. Altera presents Arria devices as supporting PCI Express (x1 and x4), Gigabit Ethernet and Serial RapidIO standards at speeds up to 2.5 Gbps; there are five devices ranging from 21,580 to 90,220 LEs (logic elements), up to 4.5 Mbits of embedded memory and up to 176 multipliers. Altera built them in flip-chip packages for optimal signal integrity.

One of the aspects of this drive for high-speed serial interfaces is that in practice, engineers are embedding it into designs, and getting it to work on boards, with relatively few problems—in terms of designers getting the technology to work on the board. All of the vendors, when asked about their applications-support experience of introducing high-speed serial I/O, offer a similar account, typified by the response of Giles Peckham, European marketing manager at Xilinx: “[Although] the market has grown very fast, customers have integrated the technology without any real issues.” Recognising that many engineers will implement a serial interface without needing the ultimate speed it offers, Xilinx offers Aurora, a free-download, “lightweight” link-layer protocol. You can use it in any application that requires serial point-topoint connectivity, rather than one of the standards which, as Xilinx says, “can prove to be overkill for many applications” that require simple point-to-point connectivity. Aurora is a scalable, open protocol that you can implement in any silicon device or technology. It provides a transparent interface to the physical serial links, allowing upper layers of proprietary or industry-standard protocols—such as Ethernet and TCP/IP—to use these highspeed serial links, while the protocol employs the minimum amount of logic.

LOW-POWER-CHIP OPTIONS

A further dimension of the programmable- logic equation is power, an area to which Actel has devoted considerable effort, leading up to its announcement of the ProASIC3L family in January 2007. Power has become a multi-dimensional design challenge, according to senior vice president Fares Mubarak: not just a matter of the optimum silicon and process design, but a complete-system problem. Mubarak presents the company’s offerings as a spectrum, from ProASIC3 for performance down to the Igloo range for lowest power. ProASIC3L is in the centre of that spectrum; Mubarak says that for this design the silicon process stays the same as that of the parent ProASIC 3 family, but design changes cut power by up to 40% for dynamic and 90% for static power. The family is flash-based with upto- 350-MHz operation.

In common with the 5-W IGLOO FPGA family, the ProASIC3L devices support a 1.2V core voltage and the FlashFreeze feature to quickly switch the device from dynamic operation to static without switching off clocks or power supplies. Mubarak is among many managers in the sector who note that—for many designs—performance is often no longer the most critical aspect of a design. Whereas for a long time the overriding objective of FPGA-design-tool suites was to achieve timing goals, power now joins timing as a principal aim. With Actel’s version 8.1 release of its tools suite, late in 2007, a number of new features appeared to support minimum-power design. Carrying out place-and-route around specific clock spines within the chips—power-driven, as opposed to timing-driven, place and route—sees an average 13% reduction in power, Mubarak claims. Similarly, he sees a specific role for the company’s Fusion devices as power-management chips that are in themselves low power.

All this fits with the vision of Actel CEO John East: energy efficiency has become a key goal, and in his view a piecemeal approach is inadequate: “To get power efficiency, you need to do everything efficiently—and that includes ‘electronic stuff’ in general. It’s part of the problem, and its [importance is] growing fast. We are locked on to the path of shrinking silicon dimensions, and it’s making the power problem worse.”

As a related issue—making systems in general more energy-efficient—East is looking to automotive markets as a growth sector, declaring: “Automotive will embrace programmable technology with vigour.”

All of the programmable-device vendors share this view: each of them regards, with some relish, the potential volume business that would come with design wins in automotive. At Altera, Chawla cites it as one of the alternative markets the company is pursuing to relieve the dominance of communications (in the European region)—others being the industrial sector, and, interestingly, military systems. “Military is an area that we more or less left about 12 years ago, but we are seeing more and more activity there.” He cites specific disciplines, in which designers are using device families such as Cyclone, as being particularly applicable to the sector.

Similarly, to lower barriers-to-adoption in the automotive sector, Xilinx has announced an automotive-ECU development kit for “infotainment” applications, in conjunction with German automotivesystem developer Si-Gate. Based around the Spartan 3E low-cost FPGAs, the XA automotive ECU kit, Xilinx says, provides a platform for rapid development of invehicle networking, infotainment, driver assistance, and driver-information systems. The kit includes a development board with pre-engineered hardware interfaces, supporting existing automotive-application intellectual property (IP).

The XA1600E development board has an XA Spartan-3E 1.6-million-systemgate FPGA, and on-board hardware interfaces such as CAN 2.0B and C, Ethernet 10/100, USB 2.0, SPI and SCI. Pre-verified Xilinx and third-party application IP provides the building blocks for developing MOST systems or FlexRay connectivity, along with high- and lowspeed CAN bus interfaces. The kit also includes versions of the Xilinx Embedded Development Kit and supports ISE design tools. The XA Spartan-3E family is AEC-Q100-qualified and comes in five device densities from 100,000 to 1.6 million system gates with various package options. XA devices are available in both extended-temperature Q-Grade (40 to 125°C Tj) and I-Grade (40°C to 100°C Tj).The XA Automotive ECU Development Kit costs $1495.

At all the programmable-device vendors, provision of pre-qualified IP, whether it originates from within the respective company or from third parties, has also become a priority. Much of it is application- specific, but perhaps the flagship piece of IP that has generated attention in recent months is the ARM Cortex M1 processor core. Actel led the way with ARM with its implementation of, firstly, ARM7, implemented under the security features on its FPGAs; and more recently, Cortex M1. John East, speaking of applying the microcontroller cores to general control tasks, says, “With ARM7 [not optimised for implementation on FPGA] we got 25 MHz, which was underpowered. With Cortex M1, we get 50 to 75 MHz, which is ‘enough’.” The ProASIC3L family also supports the free implementation of a Cortex-M1.

Altera also has a package solution for Cortex M1 (Reference 1). For around $5000, you get a bundled solution of tools and a development and deployment licence to build the core on Altera’s FPGAs. Ro Chawla, at Altera Europe, notes that while his company has had interest in the concept, the package—for which distributor Arrow is the sales channel—has until now only been widely available in the US. He expects it to be more readily available here in Europe in 2008.

IP GOES FREE

Typical of an IP announcement supporting the industrial design sector is a recent introduction from Xilinx: 10/100 Ethernet MAC Lite, single-precision floating-point-unit, industry-standard- UART (universal asynchronous receiver/ transmitter) 16450/16550-controller-and- IIC (inter-integrated circuit) interface IP cores now incur no licensing charges. In its Embedded Development Kit (EDK), Xilinx has ported the four IP cores to the enhanced on-chip CoreConnect bus structure, the Processor Local Bus version 4.6 (PLB46) that the company introduced in November 2007, for designs using the MicroBlaze soft processor and the PowerPC processor embedded in the Virtex family of FPGAs. Xilinx says that the EDK now includes over 40 cores for licensing at no charge: the catalogue also includes cores for which a licensing fee applies, such as a Tri-Mode Ethernet MAC, USB2 and CAN (controller area network) core, and the FlexRay controller. The EDK itself, version 9.2, costs $495 and includes the MicroBlaze v7 processor core with an optional MMU (memory-management unit), Xilinx Platform Studio (XPS) 9.2 tool suite, software drivers, documentation, and reference-design examples.

REFERENCES

Graham Prophet, “ARM’s Cortex-M1 now on Altera,” EDN Europe, November 2007, pg 18, www.edn-europe.com/ article.asp?articleid=1842.