Existing chips do not meet needs of battery-power portable-device designers, says SiliconBlue
EDN Europe, 02 Jun 2008
How do you make an entry into a market sector which is dominated by two major players, and in which there is already a number of other players chasing the leaders? According to FPGA newcomer SiliconBlue, you target a sector that none of the existing players is properly serving – in this case, ASIC-replacement for portable, battery-powered devices. Using a conventional FPGA architecture – a look-up-table (LUT) structure – and exploiting the features of the low-power variants of today’s 65-nm CMOS processes, SiliconBlue says that it can now built an FPGA with on-chip non-volatile memory, that has low static and dynamic power, without the need for entering special low-power modes. The architecture, which it calls iCE, is a conventional, SRAM-based, 4-LUT/register/fast carry (original patents held by Xilinx having expired, SiliconBlue notes) format with additional on-chip non-volatile memory in the form of an adaptation of the technology developed by Kilopass. This is an anti-fuse one-time programmable technology that employs oxide-rupture: for its similar technology, Kilopass claims a very high level of IP security – the programmed memory cells are buried deep in the diffusion and cannot be reverse-engineered or read-out optically. In a FPGA, this NV memory (called NVCM) will load the SRAM configuration memory all within the chip. SiliconBlue says it has re-designed the fundamental architecture from the “ground up” for low-power operation. It uses, for example, register files for block RAM, using 500 nA per 4k bits; and the IP for mobile DDR memory for pow-ower LVDS drivers. SiliconBlue’s first chip, the iCE65L04, is sampling now in volatile-memory form (ie, without the NV memory layer) and will be available in NV form in October 2008. It has 3520 logic cells, a maximum of 176 I/Os, an operating current as low as 50 μA and a target high-volume price of $2.00. The company will follow that with chips half as large (L02), and twice as large (L08), in a programme that aims to have all three on the market in NV form by March 2009. SiliconBlue’s chart for packaging also refers to an L16 version – presumably twice as large again – for which it has not released timing. Packaging options range from a 12 x 12 mm BGA on 0.5-mm pitch, down to a 3 x 4-mm chip-scale package with 0.4-mm pitch. Packages with different I/O counts use common sub-/super-set pin layouts so you can move up or down in complexity on a single board layout. The tool flow is called iCEcube and is a VHDL and Verilog-based development environment that wil the company says, be familiar to ASIC designers while being accessible to those more familiar to FPGA design tools. Synthesis and placement are provided by Magma Design Automation (there is an FPGA engine within the synthesis flow) while SiliconBlue developed routing and bitgen were aspects. The tools include a power estimator spreadsheet for estimating total power of a design. The iCEman65 includes an iCE65L04, and is an evaluation kit that provides a complete platform for low-power testing and application development. You can use the chips in re-programmable mode, bypassing the NV memory, both before and after you program the NV memory; once you complete development, a security setting isolates the SRAM so that it can only load from NV memory and cannot be read externally. The chip can self-boot from one of four external (serial) channels. Reflecting the focus on power, the development board includes the facility to intercept power rails for the core and I/O regions of the chip, to verify where all of the power is consumed. The four separate I/O banks can all run from separate power rails, making the chip ideal for logic-plus-level-shifting interface applications, the company says. In the first instance SiliconBlue is a fabless chip supplier; if a large-system-on-chip builder had the need for block of low-power programmable logic on his SoC, an IP business model is also possible, a company spokesman said.