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FPGA start-up challenges in low-power sector

How do you make an entry into a market sector that two major players dominate, and in which there are already multiple players chasing the leaders? According to FPGA newcomer SiliconBlue, you target a sector that none of the existing players is properly serving—in this case, ASIC-replacement for portable, battery-powered devices. Using a conventional FPGA architecture—a lookup- table (LUT) structure—and exploiting the features of the low-power variants of today’s 65-nm CMOS processes, SiliconBlue says that it can now build an FPGA with onchip non-volatile memory that has low static and dynamic power without requiring special low-power modes. The architecture, which the company calls iCE, is a conventional, SRAM-based, 4-LUT/ register/fast-carry format (original patents held by Xilinx having expired, SiliconBlue notes) with additional on-chip non-volatile memory that’s an adaptation of the technology that Kilopass developed. This nonvolatile one-timeprogrammable memory structure employs anti-fuses and oxide-rupture techniques, for which Kilopass claims a very high level of IP security –the process buries programmed memory cells deep in the chip’s diffusion, safe from reverse-engineering optical examination. In a FPGA, this NV memory (called NVCM) will load the SRAM configuration memory, all within the chip. SiliconBlue says it has re-designed the fundamental architecture from the “ground up” for low-power operation. It uses, for example, register files for block RAM, using 500 nA per 4kbits; and the IP for mobile DDR memory for lowpower LVDS drivers.

SiliconBlue’s first chip, the iCE65L04, is sampling now in volatile-memory form (ie, without the NV memory layer) and will be available in NV form in October 2008. It has 3520 logic cells, a maximum of 176 I/Os, an operating current as low as 50 μA and a target high-volume price of $2.00. The company will follow that with chips half as large (L02), and twice as large (L08), in a programme that aims to have all three on the market in NV form by March 2009. SiliconBlue’s chart for packaging also refers to an L16 version—presumably twice as large again— for which it has not released timing. Packaging options range from a 12X12 mm BGA on 0.5-mm pitch, down to a 3X4-mm chipscale package with 0.4-mm pitch. Packages with different I/O counts use common sub-/super-set pin layouts so you can move up or down in complexity on a single board layout.

The tool flow is called iCEcube and is a VHDL and Verilog-based development environment that will, the company says, be familiar to ASIC designers while being accessible to those more familiar to FPGA design tools. Synthesis and placement are provided by Magma Design Automation (there is an FPGA engine within the synthesis flow) while SiliconBlue developed the routing aspects. The tools include a power estimator spreadsheet for estimating the total power of a design. The iCEman65 includes an iCE65L04, and is an evaluation kit that provides a complete platform for low-power testing and application development. You can use the chips in re-programmable mode, bypassing the NV memory, both before and after you program the NV memory; once you complete development, a security setting isolates the SRAM so that it can only load from NV memory and is impossible to read externally. The chip can self-boot from one of four external (serial) channels. Refl ecting the focus on power, the development board includes the facility to intercept power rails for the core and I/O regions of the chip, to verify each block’s power consumption. The four separate I/O banks can all run from separate power rails, making the chip ideal for logic-pluslevel- shifting interface applications, the company says.

In the first instance SiliconBlue is a fabless chip supplier; if a large-system-onchip builder had the need for block of low-power programmable logic on his SoC, an IP business model is also possible, a company spokesman said.

SiliconBlue, www.siliconbluetech.com
Kilopass, www.kilopass.com