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FPGA tool flow synthesises designs from Simulink

The MathWorks and Mentor Graphics have collaborated on a tool flow that provides and optimised path to take hardware description language (HDL) generated by MathWorks Simulink HDL Coder into Mentor’s Precision Synthesis package. Designers who have both software suites can transfer VHDL and Verilog code to generate an optimized netlist implementation for FPGA designs; the option is available for release 2006a or later of the Precision tool, and Simulink HDL Coder. Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, Embedded MATLAB code, and Stateflow charts. Mentor’s Precision Synthesis offers push-button multi-vendor physical synthesis,
language support that includes SystemVerilog, an ASIC prototyping flow, and automatic incremental synthesis. It allows designers to cross-probe between multiple views and perform interactive static timing "what-if" analyses.