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FROM EDN EUROPE: High-density programmable logic uses dual-memory structure

Programmable-logic devices built with Lattice Semiconductor's ispXP (in-system-programmable-expanded-PLD) architecture allow you to combine nonvolatile storage of logic-configuration data with in-system programmability and unlimited reconfiguration. The architecture uses a dual-memory structure in a "shadow"-style configuration. An SRAM-like memory, backed by a nonvolatile, rewritable EEPROM, sets logic configuration. At power-up, the system copies the configuration from the non-volatile memory into the SRAM, in effect providing the configuration memory on-chip. You can read changes to the logic configuration back into the nonvolatile array; you can address either memory to make in-system programming changes. Despite the area penalty, Lattice says that it will price the devices at a level comparable to a conventional programmable part of similar dimensions, and it will include an external configuration memory. The result is more secure, because you cannot access the configuration bit stream outside the chip once you finalise it for production.

The company has applied this principle to both CPLD and FPGA devices. CPLD architecture incorporates multifunction-logic blocks where you can dedicate as much as 16 kbits of memory or 32 macrocells of logic. A family of devices offers as many as 300,000 system gates, supporting functions of as many as 136 inputs in a single logic level with clocking to 285 MHz and a logic delay of 3.5 nsec. Devices operate from 1.8, 2.5, or 3.3V power rails, and universal I/O pads accommodate any conventional logic level.

Lattice has applied the memory architecture to an FPGA configuration to provide an instant-on device that copies the configuration file in microseconds at power-up. In this case, a programmable function unit is the basic building block, and the hardware embeds arithmetic functions. This family has as many as 1.25 million system gates. The architecture distributes configurable memory, or embedded block RAM, to each function unit; you can configure this memory to make fast FIFOs. Hardware-embedded high-speed serial-interface blocks assist communications applications. These blocks can support a serialiser/deserialiser function at speeds as high as 850 Mbps in 10B/12B or 8B/10B coding.

Device support exists in the latest release of Lattice's software, and Exemplar (www.exemplar.com) and Synplicity (www.synplicity.com) will supply third-party synthesis support. Samples of both device families will be available during this or next month.

Lattice Semiconductor, +44 1932 582941, www.latticesemi.com.