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Gain-of-two sample-and-hold amplifier uses no external resistors

When you need to simultaneouslysample a signal and amplifythe signal level, you can cascade acommon gain-of-one sample-and-holdamplifier and an amplifier with a voltagegain of one. With some exceptions,such an amplifier has two external resistors(Reference 1). These resistorsdissipate power even at the steady stateof the sample-and-hold amplifier. Inmonolithic ICs, power dissipation andthe consequent generation of heat fromresistors are not the only items in thelist of the drawbacks of external resistors.Integrating precise resistors withina silicon chip requires more processingsteps, because such resistors are thinfilmNiCr (nickel-chromium) or SiCr(silicon-chromium) elements. Manufacturerslaser-trim these resistors to a tighttolerance value, contributing to the costof an IC. Because these resistors occupymore chip area than standard signalprocessingtransistors, the chip must be larger, further increasing thefinal cost. It’s no wonder thatdesigners of monolithic ICs asmuch as possible avoid usingprecision resistors.

If the required voltage-gain of a sample-and-hold amplifier is an integer, which it is in most cases, you can use an alternative way of increasing the magnitude of the output signal. For a voltage gain, G, the circuit can simultaneously track input voltage, VIN, on temporarily ground-referenced tracking capacitors. Subsequently, an interruption occurs in tracking and cancels the ground referencing of G-1 of these capacitors. Meanwhile, the tracking capacitors stack on top of each other. The voltage on the stack is the sum of voltages of all of these capacitors, and it thus has the value of GV_IN. Upon the sample command, the constant voltage of GV_IN gets stored in the G+1 groundreferenced storing capacitor.

Figure 1 shows an example of a sample- and-hold amplifier with a voltage gain of two. Voltage followers control the potentials on capacitors C₁, C₂, and C₃ using their shutdown function. The design uses Analog Devices’ (www. analog.com) AD8592 dual op amps because their output-leakage current in shutdown mode can be lower than 10 pA (Reference 2). You can follow the operation of the sample-and-hold amplifier with the timing diagram (Figure 2). The external logic-control signal, Q_S, is at a low level, and the C₁ and C₂ capacitors simultaneously track the voltage at its input. The shutdown inputs of followers A₁, B₁, and A₂ are tied together. At Q_D=high, they are enabled, so the input voltage appears at the outputs of A₁ and B₁, and no voltage appears at the output of A₂. After the high-to-low transition of Q_D, a dead slot follows with each of the controlled followers turning off. At Q=high, B₃ and B₂ turn on. Thus, the voltage in C₂ appears at the output of B₃. The potential of the input voltage occurs, therefore, at the lower node of C₁ (Pin 2 of IC₂). Because C₁’s voltage has the same value as the input voltage and the output voltage, the B₂ follower is 2V_IN. Capacitor C₃ thus charges to the voltage of 2V_IN. After the high-to-low transition of Q_S, another dead slot follows to prevent any cross-conduction in the circuit. At the next high-to-low transition of Q_S, the process repeats.

The A₃ follower serves as an impedance converter, outputting the voltage in C₃. The single NOR and AND gates, together with op amp IC₆ functioning as a delay line, modify the single external-logic-control signal to create the properly timed internal logic signals, Q_D and Q_S.

For a noise analysis, assume that the noise characteristics of each of the followers are the same—namely, the standard deviation, A, of the random component of the output voltage of a single follower. At the end of the tracking interval, both C₁ and C₂ charge to the input voltage. The standard deviation of the VC₂ voltage is σA only for the A₁ follower. The standard deviation of the VC₁ voltage is, however, √2σA, because C1 charges through two series- configured followers, B1 and A2. The standard deviation of the VC1+VC2 voltage thus has the value of 3σA. The voltage of VC1+VC2 applies to C₃ through two followers in a cascade, B₃ and B₂, within the sample interval. Further, the VC₃ voltage applies to the output through the A₃ follower. Because all of the noise sources are mutually independent and because they all effectively act in series, the standard deviation of the output voltage is σ_OUT=√6σA. Increasing the integer gain to the value of G yields √3GσA. You now pose an RSNR (relative signal-to-noise ratio) as gain, G, over a relative increment of noise at the output, yielding:

For the sample-and-hold amplifier in Figure 1, the RSNR equals 0.8165, meaning that the noise characteristics of the circuit are slightly worse than those of a single follower. For a gain of three, the RSNR has the value of one, and, starting from a gain of four, at which the RSNR is 1.155, it gradually rises with increasing gain. The conclusion is that, for voltage gains of four or higher, the noise characteristics of the sample-and-hold amplifier are better than those of a single follower.

REFERENCES

Štofka Marián, “Gain-of-two instrumentation amplifier uses no external resistors,” EDN Europe, April 2007, pg 40, www.edn-europe.com/article. asp?articleid=600. “AD8592 Dual, CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifier with 250 mA Output Current and a Power-Saving Shutdown Mode,” Analog Devices Inc, 1999, www.analog.com/zh/ prod/0,,759_786_AD8592,00.html.