High-system-integration PLDs for medium-density designs

EDN Europe, 01 Dec 2010

Lattice Semiconductor’s MachXO2 PLD family offers designers who might previously have used low-density PLDs or CPLDs, a new product configuration that increases system integration while reducing power and cost. Lattice builds the parts on a low power 65-nm embedded flash process at Fujitsu, yielding devices with from 2000 to 7000 look-up tables (LUTs). Compared to the previous XO family, there is a 3-times increase in logic density, a 10-times increase in embedded memory, more than a 100-times reduction in static power and up to 30% lower cost for equivalent functionality. Some commonly-used functional blocks that you might have had to build with LUTs in earlier parts now come diffused on to the chips; for example, user flash memory (UFM - accessed as in the organisation diagram below), I2C, SPI and a timer/counter – and that can save as many as 600 LUTs in some designs, Lattice says.

There are three variants; ZE devices range from 256 to 7K look-up tables (LUTs), operate from a nominal 1.2V power supply, and support system performance up to 60 MHz. With standby power down to 19 µW and packages measuring 2.5 x 2.5mm, Lattice intends MachXO2 ZE devices for cost-sensitive, low power consumer designs.
MachXO2 HC devices range from 256 to 7K LUTs, operate from a nominal 3.3V or 2.5V power supply, and support system performance up to 150 MHz. Offering up to 335 user I/O and features including non-volatile configuration storage (in flash), input hysteresis (for noise resistance) and single-chip, instant-on operation, you might use these in control applications in telecommunications, computing, industrial and medical equipment. The third family, HE chips, range from 2K to 7K LUTs, operate off a nominal 1.2V power supply and support system performance up to 150 MHz in power-sensitive system applications.

Lattice designed the chips for maximum I/O capability with minimum PCB complexity; I/O pads are on a staggered grid, and I/O banks are asymmetric on different edges of the chips, to support designs that fan-out-or fan-in connections as they process data. You can design the chips – silicon becomes available from late 2010/early 2011 – on Lattice’s free Diamond v1.1 software (download here), that includes the company’s own synthesis tool. Or, you can use Aldec or Synplicity tools. Reference designs are provided, and a library of IP cores includes an open-source 8/32-bit MCU, and support for the Wishbone on-chip bus. Starter kits begin at $39 or $149.