IBM to build 3-D memory for Micron

EDN Europe, 02 Dec 2011

At the forthcoming IEDM (International Electron Devices Meeting) on December 5 in Washington, DC, IBM will present the details of its through-silicon-via (TSV) manufacturing process: IBM and Micron Technology have announced that Micron will begin production of a new memory device built using the first commercial CMOS manufacturing technology to employ TSVs. IBM’s TSV process will underpin Micron’s claim, for its “Hybrid Memory Cube (HMC)” of speeds 15 times faster than today’s technology. The silicon generation is IBM’s 32nm, high-K metal gate process technology.
TSVs are electrically7 isolated conducting channels that pass through the full depth of the silicon substrate. When dice are mounted directly on top of one another, they permit direct connection from the few Angstroms-depth of active diffused circuitry on the top surface of a die, to the corresponding active devices on the next die below. Prior to TSVs, vertically-stacked dice use wire-bonding either chip-to-chip or via the carrier substrate.
HMC uses advanced TSVs to combine high-performance logic with Micron’s DRAM. HMC delivers a claimed intra-device bandwidth of 128 GBytes/sec, Micron says, using only 30% of the energy required to drive signals off- and on-chip in a conventional layout. Footprint is also potentially reduced by an order of magnitude.
An IBM spokesman adds that the process will have “applications beyond memory….with drastic improvements in battery life and device functionality”.
“HMCgives [system] architects a flexible memory solution that scales bandwidth while addressing power efficiency,” said Robert Feurle, Vice President of DRAM Marketing for Micron.