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INTEGRATION IN THE OTHER DIRECTION

BUILDING YOUR SYSTEM WITH SEPARATE DICE OR SEPARATE CHIPS MAY BE A SMART ALTERNATIVE TO USING SoCs.

SoCs (Systems on Chips) have historically represented the Holy Grail for electronics because using these chips allows electronic-systems designers to pack a lot of digital circuitry into a small area. Nevertheless, fine-line CMOS does not suit use in analog, power, and RF functions, and tiny CMOS transistors are prone to noise and leakage problems. Further, the dedicated mask set that you need to make the chip can cost more than $1 million. You then must commit to that design until high-volume sales amortize its costs. For these reasons, it sometimes makes more sense to use separate chips rather than pack everything onto one.

Dave Robertson, vice president of analog technology at Analog Devices, advocates employing “smart partitioning” rather than dictating a dogma for either integration or “disintegration”— that is, moving functions onto other chips. “You have to look at each case and pick the smart thing to do,” he says. “The smart thing to do in 2010 was not the same smart thing to do in 2007 and may not be the same smart thing to do in 2013.” From a historical standpoint, no company would better exemplify the mistakes of choosing the wrong strategy for integration than Trilogy Systems, whose goal was to put an entire mainframe onto one wafer—the precursor of today’s SoC. The company’s $230 million in venture-capital funding was the “biggest start-up kitty ever,” according to Myron Magnet, a former reporter for Fortune and now editor-at-large of City Journal (Reference 1). Trilogy eventually collapsed and became one of the biggest failures in Silicon Valley history after yield problems forced designers to implement redundant and corrective circuitry. This circuitry took up even more space, and the designers soon realized the near impossibility of testing such a gigantic system.

In other words, massive integration is not always the best option. “We look at what technology best fits,” says Tim Kalthoff, chief technologist at Texas Instruments. “Sometimes, it makes more sense to use one die; other times, using multiple dice makes more sense.”

Digital functions, such as memory cells, which require more process steps than CMOS logic can provide, also may benefit from a disintegration approach. For example, Samplify Systems makes ADCs with built-in data compression but implements analog functions, such as the low-noise amplifier for ultrasound, off-chip (Reference 2).

SiTime offers MEMS (microelectromechanical- system) oscillators that use clever leading-edge process technology that involves laying down silicon structures inside silicon oxide, or glass, capping the structure with polysilicon, and then dissolving the glass with hydrofluoric acid to create the cantilevered oscillator structure (Reference 3). The silicon process has circuitry on the same die to perform signal conditioning and other functions. It would make no sense, however, to implement all these process steps in a fine-line digital process so that you could integrate a MEMS oscillator onto an ASIC or an FPGA. This approach would invoke a cost penalty that would apply to the entire die.

The extra process steps for MEMS, analog, or memory also reduce the yields of the fine-line digital circuits. “We have MEMS parts with the sensor and signal conditioning on the same substrate,” says Robertson. “In other parts, we disintegrate the sensor from the signal conditioner and put two substrates into one package.”

Silicon transistors are not the best optotransistors because silicon has an indirect bandgap, which can reach maximum efficiencies of only 22% compared with 41% for direct-bandgap materials, such as GaAs (gallium arsenide, Figure 1). Researchers are trying to mix these processes by placing both germanium and gallium semiconductors onto a silicon die (Reference 4). Even if this research succesfully transfers to the real world, it will still be uneconomical to add the required process steps to large CMOS digital die.

In addition to their optoelectronic properties, GaAs semiconductors have higher electron mobility and larger bandgaps, which make them suited for use at RF frequencies. Cree, for example, cross-pollinates its expertise in III-V semiconductor LEDs; these semiconductors, in their intrinsic form, comprise atoms of one element belonging to Group III of the periodic table and of one element belonging to Group V. This cross-pollination takes advantage of the higher frequency capabilities of the process, and the company can apply research breakthroughs to its business lines.

NOT READY FOR SoC

Faster processes always challenge silicon in the design of RF parts. The chips in a 2.4-GHz Wi-Fi hot spot almost certainly use just fine-line CMOS. When operating at 2.4-GHz and higher frequencies, however, transistors for digital processes have poor linearity, and the low-voltage range of fine-line CMOS means that your analog circuits will have little or no head room to compensate for that poor linearity (Reference 5). These limitations are among the reasons that many companies use a SiGe (silicon-germanium) process instead of a small CMOS process (Reference 6). Small CMOS transistors have thin oxide layers and therefore must run at low voltages. This approach works well in digital designs because the lower voltages also reduce power requirements. Many RF functions require you to broadcast RF, however, in turn requiring higher voltages than you can get from a fine-line CMOS process.

You can reduce the high leakage of fine-line CMOS by using a dielectrically isolated silicon process, but that approach eliminates the technology’s cost advantage. Because glass conducts 10 times less heat than crystal silicon, using glass to provide the dielectric isolation may cause a thermal problem. For this reason, Peregrine Semiconductor and others put CMOS onto a crystalline sapphire substrate that conducts heat three times better than glass. The lack of a silicon substrate also makes these companies’ chips resistant to radiation.

Hittite Microwave bases its decisions about the level of integration on such factors as process capability; engineering talent; and market requirements, such as cost, volume, and design volatility. For example, the company makes high-performance microwave-synthesizer modules that use three processes in separate dice to provide the best performance (Figure 2). The company also makes PLL (phase-locked loop) parts that integrate two dice in one QFN package, using a GaAs process to get the best performance for the VCO (voltage-controlled oscillator) and a silicon die for the PLL function. Hittite believes that it is appropriate to use a CMOS IC if the application demands the low cost and compactness that consumer and end-user applications typically require. For example, a vehicle’s radar detector typically uses one CMOS chip because the cost pressures make that approach the only viable one. Hittite’s line of PLLs integrates CMOS operating at frequencies lower than 6 GHz and integrates a multi-die part for higher frequencies. Using GaAs, on the other hand, enables you to implement VCOs that operate at frequencies as high as 26 GHz.

According to Steve Sockolov, analogproduct- line director of precision amplifiers at Analog Devices, basic electrical reasons exist for implementing separate chips for different functions. “We have amplifiers at the edge of the board or on a connector, where customers demand 8-kV ESD [electrostatic-discharge] ratings,” he says. “You can put those large ESD structures on a fine-line process, but it would not justify the cost.” Many customers also demand power-supply overvoltage ratings of 40V, which fineline processes cannot deliver, he notes.

Hubert Engelbrechten, chief executive officer at analog-signal-processing startup GTronix, notes that using separate chips for signal conditioning saves power and reduces latency (Reference 7). The read-head amplifiers in disk drives, for example, must be on the moving read head to reduce noise and lower the impedance of the signal to the rest of the system.

The laser-driver chips in DVD players also must reside on the moving optical-power units because the units’ location close to the load minimizes the trace inductance between them. Fairchild employs this principle in its DrMOS (driver-metal-oxidesilicon- field-effect-transistor) parts. Incorporating the driver in the same package as the power FET improves switching speed.

ADSL (asymmetrical-digitalsubscriber- line) amplifiers from Analog Devices work with transformers that must send 40V signals across twisted-pair phone lines (Figure 3). Using a large step-up transformer to perform this task would allow the use of low-voltage amplifiers but would also decrease the incoming signal and system perform ance. The Analog Devices ADSL amplifiers instead operate from 12 or 24V so that the transformers can keep a nearly 1-to-1 ratio of primary to secondary windings. The ADSL drivers also provide protection from lightning strikes on the phone lines, which can turn into 1-msec, 6A surge currents at 30 to 50V. A CMOS-process-derived part could not withstand surges of this magnitude, says Jim Doscher, product-line director of high-speed networking amplifiers at the company.

You must also consider the requirements of your system when you implement multiple chips. “You don’t want to run a regulated voltage across the hinge of a cell phone,” says Dan Swan, standard-power-product-line director at Analog Devices. The benefit of placing voltage regulators close to the load is equally valid in large data servers with hundreds of power-supply rails, he adds.

“For both performance and power consumption, we’ve proved that a disintegrated analog front end with two processes can gain from both worlds,” says Danny Kreindler, director of marketing for medical and imaging products at Samplify Systems. Samplify integrates 16 ADC channels—but not the analog lownoise and programmable-gain amps— into one chip. Vendors of single-chip products tried to convince customers that using one chip would be less demanding because this approach uses fewer components, simplifies the design, and relieves customers of worries about impedances and coupling. “The single-chip vendors would say, ‘Here is a chip and data sheet. Go!’” he notes. “It worked to get people to design in the chips, but I now see customers designing out single-chip solutions after seeing that [the other approach] looks good only on paper.” Kreindler adds that a multichip system can achieve lower power consumption, often with a smaller board, than a single-chip approach. Samplify is countering the easeof- design issue by offering demonstration boards and software that allow customers to evaluate their systems.

Power savings is another reason for choosing disintegration. “You have to look at the system as a whole and think of the best way to save power for the entire system,” says Analog Devices’ Swan, who provides an example in which a low-power chip can sense motion using an onboard accelerometer. The powermanagement chip in this scenario would then light the backlight and enable the circuitry that detects that a user is activating a key. In that way, you would waste no power running the big digital chips until you need them. For the same reason, Wolfson Microelectronics partitions handset electronics to incorporate an audio subsystem and the power management onto one analog IC.

Even in the purely digital domain, cell-phone designers divide systems into two large chips: the baseband processor and the application processor. The RF baseband chip is a real-time operating system that demands low latencies and lack of interruptions. The application processor can act more like the operating system on your desktop, in which millisecond latencies are not problematic. “The baseband chips are so busy doing error correction and demodulation of these complex protocols that a separate chip must do the user functions,” says Paul Greenland, a power-management consultant. Greenland notes that you cannot use the voltage and current characteristics of tiny fine-line CMOS transistors for many analog functions. “You can make a digital PWM [pulse-widthmodulated] loop in one-fourth or onesixth the die area of an analog PWM loop,” he says, noting that digital power is ideal in some medical and industrial markets. In these applications, digital power can provide the margining and fine control, but this approach involves a development-cost issue. For example, an 8-in. fine-line CMOS mask set costs $1.2 million to $1.4 million, meaning that your digital-power chip must target highvolume markets to amortize that cost over a lot of chips.

Exar takes this approach with its digital-power chips, designed for set-top boxes and servers. The company’s IP (intellectual property) and patents often involve methods of making small dice. The manufacturer integrates the charge pump’s high-side drivers—but not the power FETs—into the chip. With such a small die, the chip can compete with analog products as well as offer all the programmability and communications capability of a digital chip.

TESTING, TESTING …

Market definition, system partitioning, and IC design are just some of the jobs that you must complete before you get a product into your customers’ hands. You must also test that product all through the manufacturing process, and this testing and the design of the test systems involved can be major parts of introducing a chip, says Jim Williams, staff scientist at Linear Technology. You cannot use inexpensive digital testers to test highend, sophisticated analog chips, such as those from Linear Technology. The probe card that holds the chip under test is often customized for that chip. “It is not uncommon for the design and building of the test system to form the critical path on the way to the release of a new part,” says Williams.

A large semiconductor company recently learned the nuances of analog testing when it moved all product testing to standard digital machines. The designers of the probe cards and test routines in the high-performance analog division had retired. With poor documentation and exotic circuits outside the knowledge of the company’s digital- test engineers, the task of running all chips on standardized testers soon turned into a disaster that took more resources than the company had anticipated.

Beyond testing, you must also consider packaging for your design. When ICs came in 40-pin ceramic packages, adding a chip to your design brought about a huge cost and PCB (printed-circuit-board)-area penalty. These days, however, the packages are no bigger than the dice inside them. Most analog-product vendors offer parts in chip-scale packages, essentially including the die and the solder bumps on the metallization to mount the part on your board (Figure 4). Putting the functions into separate parts allows for flexibility in process choice and board location that may be essential to meeting your design goals.

Many companies put many dice into one package to reap the benefits of process and die-substrate variations and the convenience and size benefits of a single package. Texas Instruments offers an ultrasound analog front end comprising two dice on one package (Figure 5). The company uses a SiGe process for low noise and CMOS for digital-processing and ADC functions. Similarly, Linear Technology sells quad op amps that comprise two dual op amps in the same package. The company recently created an RS-485 isolated-driver module that incorporates multiple chips, along with transformers for isolation and power (Reference 8). Linear Technology has also inserted many of its RF parts into micromodules, in some cases using competitors’ SAW (surfaceacoustic- wave) filters. Analog Devices, meanwhile, offers a series of isolators that uses two ICs and a separate spiral transformer. “The packaging technology has changed the rules a lot over the last 10 years,” says Robertson. “The next 10 years will see through-silicon vias and other packaging technologies change the integration rules again.”

From all these arguments and counterarguments, you can see that the goal of integration or disintegration is a moving target. If your system is in a settled market with consumer cost pressures and modest performance demands, then an integrated fine-line CMOS process is your best option. Even settled markets are dynamic, however. A Wi-Fi chip may perform the RF and digital processing necessary in today’s market. If you need a router that performs deep packet inspection to discard spam or thwart hackers, however, you may wish that you had broken that design into smaller parts (Reference 9).

Die and mask costs, process capability, and engineering efforts are all changing monthly. What is now available at your company may differ from what is available to your competitor. If your company has analog-design experts, it may be better off sticking to disintegrated designs. Your competitor, on the other hand, may decide to put everything onto one chip. The market will decide the ultimate winner, but make sure to understand all the implications of system partitioning and that every situation and every market is different. “That’s what makes the job so interesting,” says Analog Devices’ Robertson. “Even if you are attacking the same endapplication problem as you were three years ago, the toolbox changes every couple of years, so there are different ways to attack the problem, and the trade-offs become different.” System partitioning and work flow are real-world problems, and the real world is always analog, even if your system is purely digital. That fact is what makes integration and disintegration so challenging—yet so rewarding when you make decisions based on little more than intuition and the outcome is successful.