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IP core generator features radiation-tolerant math blocks

Actel has introduced the CoreFIR v4.0 IP core generator, leveraging the embedded radiation-tolerant multiply-accumulate blocks provided in the company's RTAX-DSP FPGAs. These FPGAs integrate radiation-tolerant math blocks with the spaceflight-proven industry-standard RTAX-S FPGA architecture. The core generator utilises these on-chip resources to implement an enhanced parameterisable, single-rate, enumerated FIR (Finite Impulse Response) filter, delivering the essential building blocks in DSP systems. The antifuse based RTAX-DSP devices are radiation tolerant and do not require complex multi-chip implementations to mitigate radiation effects in space. This reduces power-consumption, thermal loading and design complexity, while increasing overall system reliability, claims the company.

By taking advantage of the core generator and the FPGAs, designers can design and implement DSP functions while taking advantage of the company’s RTAX-S architecture. The IP core generator features parameterisable Direct core RTL generator; advanced performance, single-rate, enumerated MAC filter: configurable from two to 240 taps in devices with up to 120 math blocks, from 2 to 18bits input data precision, from 2 to 18bits coefficient precision, signed or unsigned data and coefficients, up to 46bit accumulator width, coefficient symmetry optimisation, runtime reloadable coefficients, and multiple coefficient sets or fixed coefficients; and the core runs up to 130MHz in the RTAX2000D, and the RTAX4000D RTAX-DSP family.