•  
• EDN Europe MAGAZINE
•  
• Free SUBSCRIPTION
• Subscription Renewal
• View Media Kit

• EDN
• EDN Australia
• EDN Asia
• EDN China
• EDN Japan

Logic-analyzer-based instruments debug, validate MIPI physical layer

Agilent Technologies believes that verifying, debugging, and establishing D-PHY (500-Mbps-physical- layer)-based products’ specifi cation conformance and interoperability requires specialized tools and that the logic analyzer is the correct platform on which to base such tools. Logic analyzers may at fi rst seem a curious choice because they work with slow and wide parallel buses rather than with fast and relatively narrow serial buses, such as D-PHY. However, serialization and deserialization readily adapt logic analyzers to the higher speed serial topology. More important, when you use logic analyzers with the appropriate software, they are the most appropriate instruments for displaying packet data in a manner that allows developers to quickly uncover the causes of deviceunder- test malfunctions.

The MIPI (mobile-industry processor-interface) Alliance’s (www.mipi.org) high-speed, lowpin- count, low-power serialinterconnect D-PHY standard originally intended to target a maximum data rate of 500 Mbps per lane. (The D in the acronym is the Roman numeral for 500.) However, the bus is capable of twice that speed: 1 Gbps per lane. Mobile devices—cell phones, cameras, music players, handheld TVs, and the like—represent a huge market for D-PHY, perhaps exceeding a billion units per year.

D-PHY’s diffi cult-to-achieve combination of low cost, low power, high data rate, and compact size bode well for its use in many other types of electronic devices, as well. Implementing D-PHY may, however, prove somewhat more demanding than implementing other high-speed serial protocols: Visibility of some signals can present challenges, and D-PHY lanes are inherently half-duplex to minimize pin count, whereas most other popular highspeed serial standards are full-duplex. You can use two D-PHY lanes to implement full-duplex communication or, if the data rate is amenable, you can reverse a half-duplex lane’s transmission direction on the fly.

Agilent’s D-PHY product- test offering comprises the N4851A analysis probe with a US list price starting at $13,561 and the N4861A stimulus probe with a price starting at $14,566. You use both units with the company’s 16900A logic analyzer. Your 16900A should include one or more plug-ins having at least 68 channels. Agilent expects large numbers of developers to require the analysis probe, whereas fewer will require the stimulus probe, which enables the logic analyzer to simulate D-PHY-based hardware. Software that accompanies the probes resides in the 16900A, enabling it to generate D-PHY-specifi c displays. Both instruments and the accompanying software support the MIPI Alliance’s CSI-2 (camera-serial-interface) and DSI (display-serial-interface) D-PHY-based protocols for mobile devices.

Agilent Technologies, www.agilent.com/find/mipi.