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Low-power, C-code-optimised 32-bit µP IP core

Cortus’ APS3 is a 32-bit microprocessor IP core that the company has engineered for very low power and small gate count, and that it has designed explicitly to run C code. CEO Michael Chapman describes the IP as a “cleansheet” design that the company created from first principles for embedded design where C code is the normal programming method—the core takes just 9.5 kgates to implement and runs at 250 MHz for 24 µW/MHz. A RISC design, it supports out-of-order execution and has both 16- and 32-bit instructions with no need to explicitly switch between the two. Describing the core at the SAME (Sophia Antipolis Micro Electronics) conference in France, Chapman outlined an ongoing project in which a customer is combining the core with a low-power RF link in a low-duty-cycle application that has a specified battery life of 15 years: “For low power and C-code, the APS3 is a better solution than any 8-bit core—and as a 32-bit core, it has a full 4-Gbyte address space.” In that class of mixedsignal system, you can integrate a description of the wireless subsystem into a single instruction-set simulation. In 0.18-µm CMOS, the core will run at 280 MHz and is available as a soft macro for both ASIC and FPGA implementation. Support comes in the form of a Gnu tool set from Microcross (www.microcross.com) and a $99 evaluation board from SoC Solutions (www.socsolutions.com)—the Cortus core itself is available from IP vendor Cast (www.cast-inc.com).

Cortus, www.cortus.com