Low-power chip design tools exchange data

EDN Europe, 23 Apr 2007

23rd April 2007 – The issue of standardisation of the format in which chip-design tools receive and exchange data and requirements for low-power designs received another twist when Magma and Mentor Graphics announced that their tool sets had successfully completed a design in which low-power requirements were exchanged in the UPF (unified power format). Mentor and Magma are both adherents to the UPF as administered by Accellera: this announcement is intended to show that inter-company tool set compatibility is established. The tools in this flow were Mentor’s Questa verification platform and Magma’s Talus IC layout suite – a combination, the two companies say, that goes from “RTL through gate level to GDS II.” UPF is, according to Accellera’s Denis Brophy, now approved in its version 1.0 form and is on track to be donated to IEEE to be ratified under its numbering system, as other Accellera standards have been.
Ranged against UPF is the competing CPF, the common power format, as proposed by Cadence, that it designed to do a similar job of automating the process of transferring requirements for low power operation between different elements of its IC tool chain. Spokesmen on both sides of this particular divide hint that the technical differences between the two are not so large, indicating that reconciling the two into a single scheme for low-power-requirements specification may be more a matter of political and business issues, rather than technicalities, between EDA vendors.
In the UPF tool flow, Magma says, inter-company tool sets have communicated design intent such as multiple power domains, automatic insertion of level-shifters for signals that cross voltage/power domains, and routing power to appropriate supply sources. Output files are also ready for verification against the same low-power objectives.