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Low power design environment for chip creation

Tool set spans complete silicon design path, adds software co-design options

Further backing its support for the Unified Power Format for exchange of power-related design data between EDA chip-design tools, Synopsys has assembled a comprehensive array of tools oriented towards achieving power-related design objectives. Under the name Eclypse Low Power Solution, the tools span system level, verification, implementation and signoff, intellectual property (IP), methodologies and services for low power chip development. Included are some existing tools, some with low-power enhancements, and some new elements. Synopsys will host a series of low power seminars as part of its promotion of the concept. Using to tools, the company says, you will able to apply techniques such as MT (multi-threshold) CMOS power gating, multi voltage, and dynamic voltage and frequency scaling (DVFS), in a less ad-hoc, time consuming, risk prone manner, requiring less manual verification and implementation. The company has based the suite on its Low-Power Methodology Manual, co-authored by Synopsys and ARM; the approach also extends to the Innovator environment for embedded software design. In that context, you can run software on a virtual platform using fast models of processors and IP blocks, annotating processor models to obtain an estimate of power consumption. You can derive the power profile over time, and monitor the effects of different software versions. It will allow you to answer questions such as, “in powering-down sections of the design, is there anything I have left on by mistake?” and “have I restored power to various blocks in the correct sequence to power-up the chip correctly?”
New features in the silicon design elements of the package include enhanced clock gating and low power clock tree synthesis, and advanced multi threshold leakage optimisation. Improved automation for power switch insertion and optimisation enables power planning exploration and “what if” analysis using IR drop and area constraints. The tools will balance clock trees to get identical clock gating even if the trees have different topologies; and will analyse power switch insertion – that would previously have required manual intervention – for optimal combinations and placements. Verification tools create a set of assertions to check for power-realted conditions, such as active signals left driving inactive blocks. The tools will also validate power sequencing automatically. The Eclypse offering is available now.